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Paper Title (use style: paper title) The Benefits of Three Dimensional
Interconnection Networks in SoC Design

Christopher Mineo
North Carolina State University
Department of Electrical and Computer Engineering
Raleigh, NC USA
chris_mineo@ncsu.edu
W. Rhett Davis
North Carolina State University
Department of Electrical and Computer Engineering
Raleigh, NC USA
rhett_davis@ncsu.edu


AbstractConstantly evolving semiconductor fabrication
technologies enable the design of faster and more complicated
systems, previously unseen to the industry. Such developments
have been hindered by the growing impact of interconnect
wiring parasitics in current technologies which cause wire
propagation delay and power consumption to become serious
bottlenecks. We have looked to three dimensional integrated
circuits for a solution to this problem, with limited success. We
have also proposed replacing dedicated on-chip interconnect
with message passing interconnection networks in order to
share costly signal routing resources. It will be shown that the
most feasible way to meet the performance, power, and design
time demands of future systems will be to combine these
solutions and use a three dimensional interconnection network
for global on-chip communication.
I.

I
NTRODUCTION

As a potential alternative to continued scaling in bulk
silicon CMOS technologies, researchers have suggested the
use of three-dimensional integrated circuits (3DICs) [1].
While 3DICs have great promise, there is some
disappointment because they have not yet been proven to
demonstrate the practical advantage over their 2D
counterparts for which 3DIC advocates have been hoping.
This work will offer an explanation for the mentioned
inefficacy, as well as suggest message passing
interconnection networks as a very important new
application for 3DIC technologies which will achieve the
anticipated performance gain. It is accepted that wiring
parasitics and interconnect delay are limiting factors in chip
performance and power consumption, and the replacement of
dedicated signal wires with interconnection networks is a
potential solution. The union of 3D fabrication technologies
and interconnection networks is what will allow designers to
break yet another performance barrier in todays chips.
A 3DIC process allows multiple dies, or tiers, to be
stacked on top of each other and packaged together as a
single chip. Each tier consists of all of the transistor and
local interconnect layers that exist in a conventional 2D chip;
however, electrical connections between metal layers on
different tiers are possible through the use of inter-tier vias.
Recent work has investigated the utility of such technologies,
showing that when compared to a similar 2D process, 3DICs
create the potential for much more functionality to be
contained within a single chip, thereby enabling the creation
of more complicated systems on a chip (SoC) in general.
Furthermore, theory and experimentation both show that
when an identical design is implemented using a 2D process
and a 3D process, the 3D design occupies less area,
consumes less power, and can typically operate at a higher
clock frequency. These advantages can be attributed directly
to the reduction in maximum and average length of metal
interconnect in 3D chips. 3DIC technologies allow the
circuit macros which compose a SoC, or functional units, to
be placed closer to one another and to be accessible from
additional directions, thus reducing the average amount of
wire needed to connect gates. This reduction in interconnect,
and therefore reduction in wiring capacitance, results in
power savings because of decreased gate loading. Shorter
wires clearly have a faster signal propagation delay than do
longer wires, meaning that 3DICs also decrease the
interconnect delay component of path delay.
One of the biggest issues plaguing researchers in the
3DIC community is that thus far we have not been able to
find applications of 3DICs that reach the magnitude of the
expected theoretical benefit in the aforementioned respects,
over comparable 2D designs. Expected wire length
reduction estimates are based on decreases proportional to
the area reduction. This work discusses the reasons that
current 3D chips do not meet such, and thus, do no make full
use of the benefits of 3DIC technologies. We propose
interconnection networks as a potential very important
application of such 3D processes. Interconnection networks
have ever increasing importance in the field of SoC design,
and are presented as the first application of 3DICs to take
full advantage of the technology, because unlike most other
circuits in use today, they are natively designed in 3D. The remainder of this paper is organized as follows:
section II discusses wire length and performance advantages
in present 3D designs, and section III goes into the difference
between natively 2D and natively 3D designs. It discusses
the importance of interconnection networks in general, and a
novel VLSI implementation methodology of interconnection
networks. Section IV describes the Matlab code written and
the experiments and simulations carried out. Section V then
evaluates the results of the mentioned simulations, and we
summarize our findings in section VI.
II.

W
IRE
L
ENGTH IN
3D

C
HIPS

A.

Theoretical Wire Length Reduction
When implementing an identical design in 2D and in 3D,
both with the same netlist of connectivity, we expect the 3D
version to show a substantial reduction in wire length. If we
assume that the translation to three dimensions only
alleviates routing congestion, ignoring the die area overhead
required for the insertion of inter-tier vias, we can presume
that the chip area in an n</i>-tier 3D process is 1/n times the area
required in the conventional 2D process. This assumption is
made in [2], which goes on to say that theoretically at best
the average wire length will decrease proportionally, that is,
it will decrease by a factor of 1 ( 1 / n
½
). Other research
summarized in [2] supports this using Rents Rule,
predicting similar wire length savings. Furthermore,
simulation has shown that recent 3D cell place and route
physical design tools are capable of achieving such goals;
work cited in [2] shows wire length reductions of 11% and
41% when optimizing for minimal via count and wire length,
respectively, when running benchmarks from ISPD 98.
The problem remains, however, that a number of similar
experiments have been carried out in which practical and
current designs we have not experienced such significant
benefits from 3D technologies as these predictions would
suggest. Two notable such examples have been designed
within our research group. The first, a fast Fourier transform
(FFT) chip was designed as a low power application, and the
second, a dual-core RISC processor was designed as a high
performance application.
B.

Experimental Wire Length Reduction
The first example design was created to test the 3DIC
design flow for complex circuits, developed within our
research group. The design flow was architected to involve
the modification of traditional 2D design tools in order to
quickly and efficiently produce a 3D chip from an existing
2D circuit netlist or synthesizable HDL code. As can be seen
in Fig.1, all wire lengths were shortened in the 3D design,
but unfortunately, the average wire length was only
decreased by 17% over the 2D design, while the longest wire
length was reduced by 41%. This certainly falls short of the
42% average interconnect length reduction that our theory in
part A suggests. The dual core RISC processor faired better,
when comparing the 2D design with the 3D design we see
the critical path delay shrink by over 26%. In this case we

Figure 1.

Wire Length in the 2D and 3D FFT chip [2]
came closer to meeting our goal since we were concerned
mainly with optimizing the longest or performance limiting
path in order to achieve a higher clock rate, but we still did
not see the 42% reduction in average wire length when going
to three tiers.
There are a number of reasons that we did not see the
predicted theoretical reduction in average wire length. To
begin with, these two examples were implemented in a
180nm technology, slightly dated by todays standards. In
such technologies, one would still often find designs that are
gate delay limited or macro delay limited, as opposed to
interconnect limited. This is changing in current
technologies, however, because shrinking feature size leads
to wires with taller aspect ratios which cause coupling
capacitance to become a bigger issue. Also, shrinking
feature size results in thinner, more resistive wires. All the
while, transistors are switching faster, widening the gap
between wire delay and gate delay. It is our belief, though,
that in order to see the true wire length reduction that 3DICs
are capable of, we will need to implement designs that were
originally intended for a 3D world.
III.

N
ATIVELY
3D

D
ESIGNS

All of the designs that have been implemented using
3DICs thus far naturally have been circuits originally created
for implementation on a 2D chip, that were then ported to
3D. The folding and reorganization of 2D circuits will only
result in so much of a benefit, analogous to parallel
processing. Given access to a powerful parallel
multiprocessor machine, it w