de potential performance benets? Until
recently, practical interconnection of chip stacks was
achievable only through wire bonding at the periphery,
offering little or no benets in the way of interconnect den-
sity or reduction of parasitics. But several new technologies
offer the means to cost-effectively achieve very high densi-
ties of interconnection between chips in a stack, making
true 3D ICs a reality. IC designers must know the benets
and drawbacks of these techniques so that they can decide
whether or not their systems would work better as a 3D IC.
This article provides a practical introduction to the
design trade-offs of the currently available 3D IC tech-
nology options. It begins with an overview of tech-
niques, such as wire bonding, microbumps, through
vias, and contactless interconnection, comparing them
in terms of vertical density and practical limits to their
use. We then present a high-level discussion of the pros
and cons of 3D technologies, with an analysis relating
the number of transistors on a chip to the vertical inter-
connect density using estimates based
on Rents rule. Next, we provide a more
detailed design example of inductively
coupled interconnects, with measured
results of a system fabricated in a 0.35-
µm
technology and an analysis of misalign-
ment and crosstalk tolerances. Lastly, we
present a case study of a fast Fourier
transform (FFT) placed and routed in a
0.18-
µm through-via silicon-on-insulator (SOI) technol-
ogy, comparing the 3D design to a traditional 2D
approach in terms of wire length and critical-path delay.
Overview of vertical interconnect
technologies
3D ICs offer an attractive alternative to 2D planar ICs:
They provide increased system integration by either
increasing functionality or combining different tech-
nologies. Currently, SoC solutions limit designers to one
fabrication technology for both analog and digital cir-
cuits. The trend is to use inexpensive digital processes,
which provide less than desirable performance for ana-
log circuits, and to ofoad increased complexity to the
analog designs. Using 3D ICs allows for integrating the
best technology for a particular portion of an applica-
tion into the chip cube.
Table 1 shows a summary of different 3D intercon-
nect approaches, comparing them in terms of the
method of assembly (die or wafer scale), maximum
number of tiers (tier refers to the chips in a stack, as
opposed to the layers in a chip), pitch of the vertical
interconnect, and amount of routing resources con-
sumed on the chip. Figure 1 illustrates each approach.
Demystifying 3D ICs: The
Pros and Cons of Going
Vertical
W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu,
Hao Hua, Christopher Mineo, Ambarish M. Sule,
Michael Steer, and Paul D. Franzon
North Carolina State University
Editors note:
As 3D technologies become technologically viable, there is increasing
interest in determining the achievable payoff. This article first presents an
overview of 3D technologies and introduces the motivation for moving from
2D to 3D. It then presents a case study of a fast-Fourier-transform design to
illustrate the advantages of going to the third dimension.
Sachin Sapatnekar, University of Minnesota Wire bonded
The most common approach is wire bonded, in which
wires connect the individual die in a stack. In general,
connections between chips go through the board or chip
carrier and back to other chips in the stack; however, it is
possible to bond from chip to chip in the stack. This
approach is limited by the resolution of wire bonders (for
example, 35
µm for a 15-µm wire) and becomes increas-
ingly difcult as the number of I/Os in the chip stack
increases. Unlike other 3D approaches, wire bonds are
possible only on the chips periphery, which severely lim-
its interconnect density. In terms of chip routing resources,
all metal layers are typically needed for the bonding pads,
because the mechanical stresses require many metal lay-
ers to prevent tearing of the pad during bonding, and pres-
sure tends to destroy devices underneath the pad.
499
NovemberDecember 2005
Table 1. Comparison of vertical interconnect technologies: wire bonded, microbump (3D package and face-to-face), contactless
(capacitive and inductive), and through via (bulk and SOI).
Wire
Microbump
Contactless
Through via
Characteristic
bonded
3D package
Face-to-face
Capacitive
Inductive
Bulk
SOI
Assembly level
Die
Die
Die
Die
Die
Wafer
Wafer
Tier limit
Assembly process
Heat
Assembly
Assembly
Heat
Heat, yield
Heat, yield
process
process
Vertical
35 to 100
25 to 50
10 to 100
50 to 200
50 to 150
50
5
pitch (mm)
Metal layers
All
Top 1 to 2
Top 1 to 2
Top
Top 1 to 2
All, top
All, top
blocked by pad
(a)
(b)
(c)
(f)
(g)
(d)
(e)
Figure 1. Illustration of vertical interconnect technologies: wire bonded (a); microbump3D package (b) and
face-to-face (c); contactlesscapacitive with buried bumps (d) and inductive (e); through viabulk (f) and silicon
on insulator (g). Microbump
Microbump technology involves the use of solder or
gold bumps on the surface of the die to make connec-
tions. These bumps typically have a pitch of 50 to 500
µm but sometimes have smaller pitches. The mechani-
cal stresses of assembly are much lower than with wire
bonding, so pads require only the top or sometimes top
two metal layers, leaving lower layers free for routing or
for devices.
3D package technology
1
involves embedding previ-
ously fabricated die into a set of carrier wafers with a
xed size, enabling engineers to assemble them into a
tight cube. A layer of microbumps bond each die-carri-
er tier to an epoxy routing tier that brings signals to the
edges of the cube. They then laminate the tiers into a
single stack and add metallization to the sides to con-
nect the routing tiers. The 3D package approach offers
a much greater vertical interconnect density than the
wire-bonded approach, but it does not significantly
reduce parasitic capacitances because a microbump-
bonded cube must still route signals to the periphery
before sending them back to the destination inside the
cube. With the 3D package approach, it is not the
assembly process but rather the heat inside the cube
that is likely to limit the number of tiers. The 3D pack-
age method enables the use of one or more chips, from
the same or from different fabrication technologies, in
each layer of the stack.
Face-to-face microbump technology
2
offers the abil-
ity to shorten the wires between tiers and improve per-
formance by reducing parasitics. Black et al.
determined that, with proper placement of blocks in the
3D architecture, they could reduce the use of high-
power dynamic logic circuits, repeaters, pipelined
stages, and long routing paths. This decreased overall
power consumption by 15% while simultaneously
increasing performance by 15%. This approach is limit-
ed to two tiers, however. Taking connections out of the
chip stack requires the use of this technology in con-
junction with a wire-bonded or through-via approach.
Through via
Through-via interconnection has the potential to offer
the greatest interconnect density but also the greatest
cost. Assembly occurs at the wafer level, placing a sec-
ond wafer face down on the rst wafer (face-to-face) and
subsequent wafers face down (face-to-back) as the num-
ber of tiers grows. The manufacturing process then etch-
es holes through the upper wafer into the lower wafer
and lls the holes with tungsten to provide connectivi-
ty. Before placement of the next chip, the backside of
the previously etched chip is thinned by polishing. The
top tier has tungsten vias that protrude along with cuts
for bond pads that provide power, ground, and I/O con-
nectivity. As in the 3D package approach, the assembly
process in through-via approaches does not limit the
number of possible tiers; rather, heat inside the stack is
the limiting factor. Also, in this approach, the dies are
not known to be good before assemblyso its possible
to attach a good die to a faulty one, making it necessary
to reject the entire assembly. In such a situation, yield
drops quickly with the addition of more tiers.
Bulk technologies
3
have demonstrated through-via
interconnection by rst coating the hole with an insu-
lator, achieving pitches of 50
µm. Silicon-on-insulator
(SOI) technologies
4
avoid the need for passivating the
hole by polishing the substrate away completely, down
to the buried oxide. SOI technologies have achieved the
smallest inter-tier pitches yet, on the order of 5
µm. As
for routing resources, the through-via approaches
shown in Figures 1f and 1g consume all layers in the
upper tier in addition to the top layer in the lower tier.
Contactless
Contactless or AC-coupled interconnection involves
the use of capacitive or inductive coupling to commu-
nicate between tiers.
5
This approach eliminates the pro-
cessing steps for creating inter-tier DC connectivity and
eliminates the need to route signals to the periphery,
allowing for reduced wire lengths. Also, because the
contactless approach requires only a minimal amount
of processing for chip thinning, the lack of specialized
processing steps makes it much cheaper than
microbump and through-via approaches.
Capacitive coupling
6,7
uses half capacitors formed
from the top level of metal. The density of these inter-
connects depends on the distance between the tiers, the
rise and fall times of the technology, and the dielectric
constant of the gap. Kanda et al. and Drost et al. hav