gned to process wire and pad signals generated by the
WAMUS Proportional Drift Tubes (PDT) described earlier. The wire is a negative current
source in the range of 0.5..50
µ
A. The pad is a positive current source in a range of 0.2..20
µ
A. The wire signals travel within the aluminum body of the PDT which with the wire
constitutes a wave guide of about 330 impedance. Two neighboring cells in one layer of
the PDT have a lumped delay jumper connecting the two far ends of the wires. A signal
originating at the near of one tube will take about 60 ns to propagate to the near end of the
other (Fig. III-1). Induced charge from the wire signal is collected on two pad electrodes
with about 700 pF capacitance each.
Each cell has a service board to bring high voltage to the wire and pads and to pick up
the signals. Single ended wire signals are converted to differential by a broadband
coupling transformer. Each cell has two pad electrodes, A and B connected to the FEB
separately. According to the current naming convention, pad electrode connected to the
pin closest to the wire pin is pad B. Though arbitrary, this convention is used to
distinguish the two pad signals.
DL 3855
20 ns
18 ns propagation time
Fig. III-1. PDT delay jumper.
A block diagram of the Front-End Board is shown in Fig. III-2. Each board includes 24
Wire Amplifier/Discriminators and 48 Pad Amplifiers and Integrators. Depending on the
number of PDT cells, 3 or 4 FEBs and one Control Board (CB) can be mounted on each
PDT. All the wire discriminators on one FEB have a common threshold voltage controlled
by the CB. There are also two test pulsers connected via a resistor network to the wire and
pad amplifier inputs. The test pulsers generate exponential signals approximating the wire
and pad signals. The amplitude and synchronization of these signals is also controlled by
the CB. The FEB has a channel enable register which allows the enabling or disabling of
any wire channel on the board. Combined with the test pulsers, this feature allows for
remote testing of most of the functions of the FEB. The FEB has six TDC ASICs
(TMCTEG3) and 24 10-bit ADCs (ADC875) which continuously digitize the arrival times
and induced pad charges whose results are stored in digital pipelines. The digitized data is 24 Wire Amplifier/Discriminators
48 Pad Charge Gated Integrators
Six Four-Channel TMCTEG3 TDCs
24 ADC875 ADCs with two input MUXs
24 CY7C4425 ADC buffer FIFOs
24 IDT72205 L1 FIFOs
Timing
&
Control
Logic
CB INTERFACE
READ
WRITE
Pad
Test
Pulser
Wire
Test
Pulser
Wire 1
Pad A1
Pad B1
Wire 24
Pad A24
Pad B24
TRESHOLD
WTSA
PTSA
WTRS
TRIGGER
Fig. III-2. Block diagram of 24-channel muon PDT Front-End Board. Muon Electronics Technical Deisgn Report, 7/23/97
59
delayed by the pipelines for about 4
µ
s which is the Level 1 trigger decision time. If a
trigger accept is generated, the appropriate portion of the time history from the pipelines is
transferred to the Level 1 FIFOs. From there information is readout under control of the
CB. The FEB also receives its timing signals via the CB interface. A detailed specification
of the FEB is provided in the Appendix A. The following sections describe different
aspects of the proposed FEB design.
A1.
Wire Amplifier and Discriminator
Wire signal discrimination is performed by the Wire Amplifier and Discriminator
(WAD). A two stage amplifier (UPC1663G and HFA1135) provides a gain of 1
µ
A/mV at
the discriminator input. A schematic diagram of the wire channel is shown in Fig. III-3.
The amplifier has a differential input which rejects common mode signals. The
transformer coupling also rejects low frequency noise. The amplifier has a rise time of 8
ns and an input noise level of 85 nA (RMS) for the bandwidth of interest. This allows us
to operate with a discriminator threshold as low as 0.5
µ
A. Additional measurements are
necessary to determine the level of a synchronous noise produced by the digital part of the
board. It is likely that this noise level will define the actual minimum threshold
achievable. L101 and C109 will be used to adjust the bandwidth of the amplifier to
optimize t resolution (discussed later). An HFA1135 has an internal limiting feature
which is used to reduce the recovery time of the amplifier when overdriven by high level
input signals. These limits are set to +3V and to - 1V respectively.
U103
U101
R105
R103
R104
R107
R118
R117
R106
R109
R113
R116
R115
R119
R111
R110
R112
R120
L101
R114
R102
R108
R101
C101
C104
C108
C107
C105
C102
C106
C109
C110
VH
WIN+
WIN-
+5
ENBL
OUT-
-5
TRSH
OUT+
WTEST
VL
U102
D102
D101
1
2
3
4
5
6
7
8
6
3
8
1
5
4
7
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
2
7
4
8
5
6
1
2
3
1
2
3
+5VA
-5VA
MAX913
UPC1663
HFA1135
MMBD7000LT1
MMBD7000LT1
+
GND
-
V+
V-
LE
V+
V-
+
-
G
G
56
100
100
180
1k
1k
180
51
100
51
51
10
51
51
10
10k
1.5u
2.2k1%
160
15.0k1%
160
0.1
220pF
33pF
0.1
0.1
0.1
0.1
2pF
0.1
+
-
V+
V-
VH
VL
Fig. III-3. Wire amplifier and discriminator.
A discriminator using the Maxim MAX913 comparator with capacitive feedback to set
the output pulse width at 40 ns is used. The 40 ns minimum width is required by the time-
to-digital converter chip to prevent false interpolator codes. This comparator has excellent
input overdrive versus delay characteristics. The 2x to 20x over threshold propagation
delay difference is less than 2 ns. The comparator has complementary outputs to match the
differential inputs of the TDC chip we have selected. This arrangement has the additional Muon Electronics Technical Deisgn Report, 7/23/97
60
benefit of less feedback to the amplifier input than single ended outputs. The power
consumption is less than 15 mA from
±
5 V supplies.
A2.
Wire Signal Triggering.
The WAMUS pads have 700 pF of capacitance which limits the noise performance and
bandwidth of their preamplifiers. Because the pad signals are unique to one tube while the
wire signals are not, due to its jumper wire, the old triggering scheme was based on the
discrimination of a differentiated pad signal integrator output. The 400 ns width of this
signal is not a problem at a crossing time of 3.2
µ
s, but is too long for one of 132 ns. The
wire signal is much faster than the pad signal, but the tube pair ambiguity problem must
first be resolved in order to use it as a trigger. The signals coming from two adjacent wires
need to be separated in order to determine which of the drift cells is hit.
A wire signal will always arrive first at the near end of the tube in which it occurred
before crossing the jumper and traveling the full length of the adjacent tube and appearing
at its near end. To determine first arrival, a simple two D-type flip-flop separator circuit
clocked by the wire signals with cross-connected Q-bar outputs to D inputs is used. Both
flip-flops are reset 60 ns after the output signal is generated. Fig. III-4 shows this
arrangement. When the difference in arrival time is less than the propagation delay and
setup time of the flip-flop this scheme breaks down. Replacing the existing far end jumper
with a delay line of 20 ns solves this problem. The custom delay line, a DL3855 from
Datatronics, is matched to the 330 ohm tube impedance and is referenced to ground with
HV capacitors. The rise time of the delay line is about 7 ns. A prototype separator circuit
based on ALTERA EPX740 PLD chip has been tested and the resolution time of the
circuit is shown in the Fig. III-5. It is clear that selected delay line provides enough time
for such a circuit to separate two signals.
R1
C1
Q
CP
Q
PR
CLR
D
Q
CP
Q
PR
CLR
D
OUTPUT 2
OUTPUT 1
WIRE 2
WIRE 1
Fig. III-4. Wire signal separator. Muon Electronics Technical Deisgn Report, 7/23/97
61
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
0
20
40
60
80
100
120
140
-5
-4
-3
-2
-1
0
1
2
3
4
5
Delay [ns]
B
Output 1
J
Output 2
Fig. III-5. Wire signal separator time resolution.
Fig. III-6 shows the response of the wire signal separator with this delay installed on a
pair of test tubes measured using the old analog TVCs on cosmic rays. Scintillation
counters were located at the far end of the drift tubes which guarantees the minimum time
difference between two wire signals. Fig. III-6a shows the t distribution without regard to
the separator output. Fig. III-6b and Fig. III-6c show the same data qualified by the
separator outputs. There is clean separation between the two tubes. The proposed circuit
will produce valid result only with one track crossing two paired PDT cells. In the rare
case of two particles crossing paired cells and generating wire signals within time
resolution of the separator (60 ns), the latest signal will be suppressed and no trigger signal
will be generated for this wire. An off-line analysis can identify and flag such events after
track reconstruction.
1400
1650
1900
2150
2400
2650
0
20
40
60
80
100
1400
1650
1900
2150
2400
2650
0
20
40
60
80
100
1400
1650
1900
2150
2400
2650
0
20
40
60
80
100
ADC counts
42 ns ec
a)
b)
c)
Fig. III-6. t distribution with a 10 x 10 cm
2
trigger scintillator at one
end. a - all signals, b - wire 1 tag, c - wire 2 tag. Muon Electronics Technical Deisgn Report, 7/23/97
62
FRONT END BOARD
ADC SEQ2
ADC SEQ1
BEAM XING
REGISTER
L1.0 DATA
Td
Td
Td
11
10
9
8
7
6
6
6
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
T=Td
SEPARATOR
SIGNAL
WIRE
THRESHOLD
WIRE1
WIRE2
DELAY
T=Td
DIGITAL
SET
53 MHz
L1.0 DATA
DELAYED X
ONE-SHOT
WIRE DISC.
XING
to TMC
to TMC
ONE-SHOT
DIGITAL
SET
53 MHz
T=Td
ONE-SHOT
DIGITAL
SET
53 MHz
C
D
D
A
A
Fig. III-7. Wire signal trigger logic block diagram and timing.
A block d