Fremont, CA 94538, USA
Tel: 510-249-6318, Fax: 510-249-1150, e-mail: lghenry@oryxinstruments.com
(3)

Barth Electronics Inc., 1300 Wyoming St., Boulder City, NV 89005, USA
(4)

Lucent Technologies, 555 Union Blvd., Room 23R-255ES, Allentown, PA 18103, USA
(5)

Micron Technology Inc., 8000 South Federal Way, P.O. Box 6, Boise, ID 83707-0006, USA
(6)

Fraunhofer-Institute Reliability and Microintegration (IZM), Hansastr.27d, D-80686 Muenchen, Germany
(7)

KeyTek, One Lowell Research Center, Lowell, MA 01852-4345, USA
(8)

IBM Microelectronics, 1000 River St., Dept. E71/ZIP967J, Essex Junction, VT 05452, USA
(9)

Advanced Micro Devices, One AMD Place, P.O. Box 3453, M/S 66, Sunnyvale, CA 94088, USA
Abstract This paper presents the results of a search for a more effective stimulus suitable for assessing the
latch-up susceptibility of integrated circuits. Different transient stimuli and amplitudes were found to have
varying effectiveness in creating a latch event. The investigation also identified the inadequate response and
recovery of existing test system power supplies and need for appropriate isolation techniques.
Introduction
The phenomenon of latch-up (LU) has existed for
many years. Identification of latch-up susceptible
integrated circuit designs is critical in this era of
increased reliability and reduced costs being driven by
the electronics industry. The majority of latch-up
characterization is performed using JEDEC Standard
No.17 [1] and JEDEC Standard 78 [2]. Through the
implementation of latch-up design rules (best
practices developed over the years to reduce/eliminate
latch-up susceptibility), devices failing to meet
JEDEC latch-up requirements at room temperature are
uncommon.
Static or dynamic stresses in various time domains
may trigger latch-up. Several studies [3,4,5] have
shown that static test methods with slowly applied
voltage or current (millisecond timeframe) do not
identify all weak devices. Although devices seem to
be robust according to standard latch-up
characterization, device latch-up failures were
occurring during accelerated stress testing (burn-in)
and in the field. These findings suggest that the static
nature of the JEDEC latch-up test at room temperature
may be a less than ideal method of determining
latch-up susceptibility. Therefore, different trigger
stimuli were investigated to help identify potentially
sensitive circuit designs
This early work served as the foundation for the
creation of the ESD Association (ESDA) Transient
Induced Latch-Up (TLU) working group WG-5.4.
The development of a new standard for latch-up
testing not only builds upon previous test standards
but also requires the collaborative efforts of many
individuals from different companies. Each
contributor brings a unique perspective derived from
experience with a particular mixture of technologies,
device applications, and test equipment. The present 3A.1.2
EOS/ESD SYMPOSIUM 99-179
ESDA WG-5.4 has members from ten different
companies and includes representatives from three
equipment manufacturers. Collection of data using
new techniques is facilitated by the sharing of known
problematic devices among the members in round-
robin testing. Identification and removal of obstacles
hindering the implementation of new automated
equipment LU stress techniques is also a major
objective for the working group.
In this paper, we first present a brief background on
early latch-up work and then review the issues
surrounding the power supply response. We then
discuss the efforts on manual and automated RC TLU
testing methodology. We also review the TLU test
results for transmission line pulse (TLP)
methodology. Finally, we discuss the results for Bi-
polar stress trigger TLU methodology.
Background
The need to implement complementary (both N-type
and P-type) transistors on an integrated circuit can
often result in current paths parallel to a desired
functional circuit. Latch-up (LU) occurs from the
activation of four-layer pnpn structures (thyristors)
that are parasitically inherent to certain integrated
circuit (IC) technologies. This undesirable parasitic
path is composed of bipolar transistors that operate as
intended under normal conditions. During abnormal
conditions, the bipolar transistors can be turned on by
a trigger stimulus. Consequently, large amounts of
current may be drawn from the power supply
producing either circuit malfunction and/or
irreversible damage. This reduction in circuit
resistance is characteristic of latch-up.
Working group WG-5.4 attempted to improve the
efficiency of latch-up screening in two different ways.
Since LU is initiated by a collection of charge carriers
at diffused layers (resistance) acting in combination
with parasitic bipolar transistors, the goal was to
maximize this charge density while minimizing the
total transferred energy. Too much injected energy
could result in thermal damage before useful
measurements could be made. This consideration and
the finite lifetime of injected carriers support the
greater effectiveness of short transients for assessing
latch-up immunity.
The collective experience within the working group
indicates that a majority of device LU sensitivity can
be triggered through power pin stressing. This is not
surprising since designers have many years of
experience in optimizing I/O buffer guard-ring layout
and computer-aided checks for appropriate
implementation. Whereas power connections must go
to every sub-circuit on the chip, the opportunity exists
to stimulate circuit structures that have not been given
the benefit of more robust layout. Therefore,
additional test efficiency can be achieved by
improving the traditional over-voltage power supply
latch-up stress.
Success was achieved on 1.5
µ
m technology devices
when robust output or power pins were stressed using
a 100nF/20 discharge network (see Figure 1).
Collaborative efforts within the newly established
ESDA working group WG-5.4 resulted in the
construction of the Model BEI-790 (
±
200 volts) RC
Pulse Generator [6]. The waveform produced is
shown in Figure 2 and was measured using a 350MHz
oscilloscope.
20
+
-
0.1
µ
µ
F
Stress
Polarity
0 to 120V
SW1
Current
Probe
S
C
O
P
E
TLU
Pulse
Output
+
-
+
-
Figure 1: First generation dual-polarity TLU pulse generator
90%
10%
Current
(mA)
Time (microseconds)
-1
0
2
3
4
5
6
7
8
9
1
Figure 2: First generation TLU waveform
Figure 3 illustrates a typical TLU test configuration
where a device-under-test (DUT) is appropriately
biased while being stressed via the dual polarity TLU
pulse generator. With several of the BEI-790
generators available to the working group, 3A.1.3
EOS/ESD SYMPOSIUM 99-180
specification issues such as pulse risetime, falltime,
and peak current amplitude were explored. During the
period from 12/95 to 9/97, these evaluations resulted
in the establishment of a TLU test method [7]. It was
quickly recognized that newer technologies (<1
µ
m)
were becoming less robust for pulses longer than
150ns in duration. On-chip ESD protection networks
generally cannot protect against this long time-
constant electrical overstress (EOS). Consequently,
many devices would be thermally damaged before a
latch-up threshold could be determined. The quest for
a new, shorter duration transient stress was then
initiated. This set-back came as a surprise to many
within the working group; proving that constantly
changing technology often results in the pursuit of a
moving target.
A
A
GND
UNDER
TEST
I
O
I/O
NOT
UNDER
TEST
I
O
I/O
V
Dual Polarity
TLU Pulse
Generator
BIAS 1
BIAS 2
DUT
Vsupply
Vsupply
Switch Matrix
1
2
+
_
+
_
D
V
D
Figure 3: Typical TLU test configuration
Power Supply Response and
Isolation
When latch-up occurs in integrated circuits, a low
impedance path is created between the power supply
and ground. Consequently, the power supply
experiences an abrupt increase in device supply
current and a sudden drop in voltage. Voltage
supplied to the device under test (DUT) must quickly
recover to near-original voltage levels to sustain the
latch-up event. In addition, the voltage supply must
limit the current to the DUT during latch-up to avoid
excessive thermal damage.
To determine whether the power supply and
connection network can meet the above requirements,
a new test was developed. The Power Supply
Response test (PSR) (Figure 4) allows for the
measurement of recovery time due to an abrupt load
change. Typical recoveries during a load change are
shown in Figure 5. The acceptable power supply
voltage response and recovery time (dark trace) is
much faster than an unacceptable power supply
response and recovery (light trace). The PSR test,
performed by abruptly changing the power supply
load from 510 to 10 , is accomplished by shorting
out the 500 resistor with a very fast and bounce-free
mercury (Hg) wetted relay. To measure the voltage
recovery (Figure 5) and current risetime (Figure 6), a
voltage probe, current transducer, and oscilloscope are
used. Power supply test data shows that the voltage of
an acceptable power supply must return to within 90%
of its initial low current level within 500ns of the
application of a load change (510 to 10 ).
Power
Supply
Under
Test
Voltage Probe
Current
Transducer
10
500
Hg
Load
Switch
Oscilloscope
+
-
Diode
Figure 4: Power supply response test circuit
100%
90%
Voltage
(V)
Time (microseconds)
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
500ns recov