REVISIONS LTR A B DESCRIPTION Increase total dose for device 01 through 04 in 1.5. Correct dimension e for case outline Y. phn Add 2.5 V configuration to the absolute maximum rating in 1.3 and recommended operating conditions in 1.4. Additional tests for 2.5 V in table I. Correct errors in case X and Y dimensions. - phn Correct dimensions for case outline X. . Correct the wording "Accelerated annealing testing" in section 4.4.4.1.1 for RHA device testing. - phn DATE (YR-MO-DA) 04-09-01 05-06-22 APPROVED Thomas M. Hess Thomas M. Hess C 07-02-26 Thomas M. Hess REV SHEET REV SHEET REV STATUS OF SHEETS PMIC N/A B 15 B 16 17 C 18 REV SHEET PREPARED BY Phu H. Nguyen 19 C 1 B 2 B 3 4 A 5 6 B 7 B 8 B 9 B 10 B 11 12 C 13 14 STANDARD MICROCIRCUIT DRAWING
THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess DRAWING APPROVAL DATE 04-08-06 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil MICROCIRCUIT, DIGITAL, GATE ARRAY, RADIATION HARDENED, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268
1 OF 19 5962-04B01 C
DSCC FORM 2233 APR 97 SHEET 5962-E284-07 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 04B01 01 Q X C Federal stock class designator \ RHA designator (see 1.2.1) / Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Generic number 1/ 06MRA010 06MRA025 06MRA050 06MRA075 06MRA100 06MRA150 06MRA200 06MRA250 06MRA300 06MRA350 06MRA400 06MRA450 06MRA500 06MRA550 06MRA600 Circuit function 10,000 gates available 25,000 gates available 50,000 gates available 75,000 gates available 100,000 gates available 150,000 gates available 200,000 gates available 250,000 gates available 300,000 gates available 350,000 gates available 400,000 gates available 450,000 gates available 500,000 gates available 550,000 gates available 600,000 gates available Signal I/O 2/ 58 192 192 308 308 308 432 432 432 432 544 544 544 544 544 Power & Ground Pads 3/ 6 48 48 76 76 76 96 96 96 96 144 144 144 144 144 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class M Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 Q or V _______ 1/ 2/ 3/ These devices are capable of being configured and support dual voltage: 2.5 V core/3.3 V or 5 V bus, 3.3 V core / 3.3 V and/or 5 V bus, 5 V core/5 V bus. The supply voltage range shall be specified in the AID. Includes 5 pins that may or may not be reserved for JTAG boundary scan. Reserved for dedicated VDD/VSS and VDDQ/VSSQ. STANDARD MICROCIRCUIT DRAWING
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SHEET B 2 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Descriptive designator See figure 1 See figure 1 Terminals 256 208 Package style Ceramic quad flatpack Ceramic quad flatpack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 4/ DC supply voltage (VDD) 2.5 Volt configuration (VDDC only) ...................................................... 3.3 Volt configuration (VDDC only)....................................................... 5.0 Volt configuration (VDDC only)....................................................... Voltage on any pin (VI/O) 5/ 3.3 Volt configuration ......................................................................... 5.0 Volt configuration ......................................................................... Storage temperature (TSTG) .................................................................. Maximum junction temperature (TJ)...................................................... Latchup immunity (ILU) .......................................................................... DC input current (II) .............................................................................. Lead Temperature (soldering 5 sec) .................................................... 1.4 Recommended operating conditions. Positive supply voltage (VDD) 2.5 Volt configuration (VDDC only) ...................................................... 3.3 Volt configuration (VI/O and VDDC) ............................................... 5.0 Volt configuration (VI/O and VDDC) .............................................. DC input voltage (VIN) .......................................................................... Case temperature range (TC)................................................................ 1.5 Radiation features. Total dose: For device 01 through 04 (Dose rate = 50 ­ 300 Rad(Si)/s) .......... For device 05 through 15 (Dose rate = 50 ­ 300 Rad(Si)/s) .......... Single event phenomenon (SEP) effective LET, no upset ................................................................................... LET, no latchup ................................................................................ Dose rate upset (20 ns pulse)............................................................... -0.3 V to 3.0 V -0.3 V to 3.9 V -0.3 V to 6.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -65°C to +150°C +175°C ±150 mA ±10 mA +300°C +2.25 V to +2.75 V +3.0 V to +3.6 V +4.5 V to +5.5 V 0 V to VDD -55°C to +125°C 3 x 105 Rads (Si) 5 1 x 10 Rads (Si) 7/ 2 128 MeV-cm /mg 8/ 6/ 6/ 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) .................................... as specified in the AID _____ 4/ 5/ 6/ 7/ 8/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. For cold spare mode (VDD = VSS), VI/O would be ± 0.3 V to maximum recommended operating condition. The dose rate shall be 50 ­ 300 Rad(Si)/s unless otherwise specified in the AID. When characterized as a result of the procuring activities request, the condition will be specified. Will be performed when specified in the purchase order. STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234 APR 97 SIZE A
REVISION LEVEL 5962-04B01
SHEET B 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. MIL-PRF-55681 - Capacitor, Chip, Multiple Layer, Fixed, Ceramic Dielectric, Established Reliability and Non-Established Reliability, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non Government publications. The following document(s) for a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DOD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 ­ IEEE Standard Test Access Port and Boundary Scan Architecture. (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents may also be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and as specified in figure 1. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET 4 3.3 AID requirements. All AIDs written against this SMD shall be sent to DSCC-VA. The following items shall be provided to the device manufacturer by the customer as part of an AID. 3.3.1 Terminal connections and pin assignments. 3.3.2 Package type (see 1.2.4). 3.3.3 Functional block diagram (or equivalent HDL behavioral description). 3.3.4 Functional description terms and symbols. 3.3.5 Logic diagram (or equivalent structural HDL description or mutually agreed to net list). 3.3.6 Pin function description. 3.3.7 Design tape # or Design document name (i.e., net list). 3.3.8 Design functional tape # or name. 3.3.9 Test functional tape # or name. 3.3.10 Timing diagram(s). 3.3.11 Fault coverage measurement of manufacturing logic tests. 3.3.12 Burn-in circuit. 3.3.13 ESD class and voltage. 3.3.14 Device electrical performance characteristics (additions to Table I). Device electrical performance characteristics shall include dc parametric, functional, ac parameters and any other data which would be considered required by a design engineer. All electrical performance characteristics apply over the full recommended ambient operating temperature range and specified test load conditions. 3.3.15 Maximum power dissipation. Maximum power dissipation shall be in accordance with the application specific design. 3.3.16 Supply voltage range. The supply voltage range shall be as specified in the AID. 3.3.17 Dose rate. The dose rate shall be 50 ­ 300 Rad(Si)/s depending on total dose requirement unless otherwise specified in the AID. 3.4 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.5 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET A 5 3.6 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.6.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.7 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.8 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.10 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.11 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 123 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING
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SHEET 6 TABLE I. Electrical performance characteristics. Conditions 1/ 2/ -55°C TC +125°C Symbol VDD = 5.0 V ± 10% VDDC = 5.0/2.5/3.3 V ± 10% unless otherwise specified VIL VDD = 4.5 V and 5.5 V Test Group A subgroups Device type Limits Min Max Unit Low-level input voltage TTL inputs CMOS inputs 3/ High-level input voltage TTL inputs CMOS inputs 3/ Schmitt Trigger, positive going threshold 3/ TTL CMOS Schmitt Trigger, negative going threshold 3/ TTL CMOS Schmitt Trigger, typical range of hysterisis 4/ TTL CMOS Input leakage current TTL, CMOS and Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold spare inputs ­ "Off" Cold spare inputs ­ "On" Low-level output voltage TTL 2.0 mA buffer TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer CMOS outputs CMOS outputs (Optional) CMOS outputs (Cold spare) High-level output voltage TTL 2.0 mA buffer TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer CMOS outputs CMOS outputs (Optional) CMOS outputs (Cold spare) 1, 2, 3 All 0.8 0.3VDD 2.2 0.7VDD V VIH VT+ VDD = 4.5 V and 5.5 V VDD = 4.5 V and 5.5 V 1, 2, 3 1, 2, 3 All All V V 2.4 0.7VDD VT- VDD = 4.5 V and 5.5 V 1, 2, 3 All 0.9 0.3VDD V VH 1, 2, 3 All 0.4 0.6 V IIN VDD = 5.5 V VIN = VDD and VSS VIN = VDD VIN = VSS VIN = VSS VIN = VDD VIN = 0 to 5.5 V VDDC = VDD = VSS = 0 V VIN = 0 V and 5.5 V VDD = 4.5 V IOL = 2.0 mA IOL = 4.0 mA IOL = 8.0 mA IOL = 12.0 mA IOL = 1.0 µA IOL = 100.0 µA IOL = 100.0 µA VDD = 4.5 V IOH = -2.0 mA IOH = -4.0 mA IOH = -8.0 mA IOH = -12.0 mA IOH = -1.0 µA IOH = -100.0 µA IOH = -100.0 µA 1, 2, 3 All -1 20 -5 -225 -5 -5 -5 1 225 5 -20 5 5 5 µA VOL 1, 2, 3 All 0.4 0.4 0.4 0.4 0.05 0.25 0.25 V VOH 1, 2, 3 All 2.4 2.4 2.4 2.4 VDD ­ 0.05 VDD ­ 0.35 VDD ­ 0.35 V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET B 7 TABLE I. Electrical performance characteristics ­ Continued. Conditions 1/ 2/ -55°C TC +125°C Symbol VDD = 5.0 V ± 10% VDDC = 5.0/2.5/3.3 V ± 10% unless otherwise specified VDD = 5.5 V IOZ Test Group A subgroups Device type Limits Min Max Unit Three-state output leakage current TTL 2.0 mA buffer TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer Cold spare inputs ­ "Off" Cold spare inputs ­ "On" Short-circuit output current 4/ 5/ TTL 2.0 mA buffer TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer Quiescent supply current 6/ 1, 2, 3 All µA -5 -10 -20 -30 -5 -5 5 10 20 30 -5 -5 50 100 200 300 50 100 150 mA VO = 0 V and 5.5 V VDDC = VDD = VSS = 0 V VO = 0 V and 5.5 V VO = 0 V and 5.5 V IOS 1, 2, 3 All -50 -100 -200 -300 IDDQ VDDC = 5.5 V 200K gates 400K gates 600K gates VDDC = 5.5 V 200K gates 400K gates 600K gates VDDC = 5.5 V 200K gates 400K gates 600K gates VDDC = 3.6 V 200K gates 400K gates 600K gates VDDC = 3.6 V 200K gates 400K gates 600K gates VDDC = 3.6 V 200K gates 400K gates 600K gates 1,3 All µA 2 1 2 3 1 M, D, P, L, R, F 1,3 All 50 100 150 2 1 2 3 1 M, D, P, L, R, F All 4 8 12 mA µA All 4 8 12 mA mA Quiescent supply current 6/ IDDQ mA See notes at end of table STANDARD MICROCIRCUIT DRAWING
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SHEET B 8 TABLE I. Electrical performance characteristics ­ Continued. Conditions 1/ 2/ -55°C TC +125°C Symbol VDD = 5.0 V ± 10% VDDC = 5.0/2.5/3.3 V ± 10% unless otherwise specified IDDQ VDDC = 2.75 V 200K gates 400K gates 600K gates VDDC = 2.75 V 200K gates 400K gates 600K gates VDDC = 2.75 V 200K gates 400K gates 600K gates Input capacitance 7/ Output capacitance 7/ TTL 2.0 mA buffer TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer Bidirect I/O capacitance 7/ TTL 4.0 mA buffer TTL 8.0 mA buffer TTL12.0 mA buffer See notes at end of table CIN COUT Test Group A subgroups Device type Limits Min Max Unit Quiescent supply current 6/ 1,3 All 50 100 150 µA 2 All 1 2 3 mA 1 M, D, P, L, R 4 4 All All All 4 8 12 17 17 17 18 23 16 19 23 mA pF pF CIO 4 All pF STANDARD MICROCIRCUIT DRAWING
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SHEET B 9 TABLE I. Electrical performance characteristics ­ Continued.. Conditions 1/ 2/ -55°C TC +125°C VDD = 3.3 V ± 10% VDDC = 2.5/3.3 V ± 10% unless otherwise specified VDD = 3.0 V and 3.6 V VDD = 3.0 V and 3.6 V VDD = 3.0 V and 3.6 V VDD = 3.0 V and 3.6 V Test Symbol Group A subgroups Device type Min Limits Max 0.3VDD 0.7VDD 0.7VDD 0.3VDD 0.6 Unit Low-level input voltage CMOS inputs 3/ High-level input voltage CMOS inputs 3/ Schmitt Trigger, positive going threshold, CMOS 3/ Schmitt Trigger, negative going threshold, CMOS 3/ Schmitt Trigger, typical range of hysterisis, CMOS 4/ Input leakage current CMOS and Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold spare inputs ­ "Off" Cold spare inputs ­ "On" Low-level output voltage CMOS outputs CMOS outputs (Optional) CMOS outputs (cold spare) High-level output voltage CMOS outputs CMOS outputs (Optional) CMOS outputs(cold spare) Three-state output leakage current CMOS Cold spare inputs ­ "Off" Cold spare inputs ­ "On" VIL VIH VT+ VTVH 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 All All All All All All -1 10 -5 -225 -5 -5 V V V V V VDD = 3.6 V VIN = VDD and VSS VIN = VDD IIN VIN = VSS VIN = VSS VIN = VDD VIN = 0 to 3.6 V VDDC = VDD = VSS = 0 V VIN = 0 V and 3.6 V. VOL IOL = 1.0 µA IOL = 100.0 µA IOL = 100.0 µA VOH IOH = -1.0 µA IOH = -100.0 µA IOH = -100.0 µA 1, 2, 3 1 225 5 -10 5 5 µA -5 1, 2, 3 All 5 0.05 0.25 0.25 V 1, 2, 3 All VDD ­ 0.05 VDD ­ 0.35 VDD ­ 0.35 V 1, 2, 3 IOZ VDD = 3.6 V VO = VDD and VSS VO = 0 V and 3.6 V VDDC = VDD = VSS = 0 V VIN = VDD or VSS All -20 -5 -5 20 5 5 µA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET B 10 TABLE I. Electrical performance characteristics ­ Continued. Conditions 1/ 2/ -55°C TC +125°C Symbol VDD = 3.3 V ± 10% VDDC = 2.5 V/3.3 V ± 10% unless otherwise specified IOS VO = 0 V and 3.6 V IDDQ VDDC = 3.6 V 200K gates 400K gates 600K gates VDDC = 3.6 V 200K gates 400K gates 600K gates VDDC = 3.6 V 200K gates M, D, P, L, R 400K gates 600K gates IDDQ VDDC = 2.75 V 200K gates 400K gates 600K gates VDDC = 2.75 V 200K gates 400K gates 600K gates VDDC = 2.75 V 200K gates M, D, P, L, R 400K gates 600K gates CIN COUT CIO Test Group A subgroups Device type Min Limits Max Unit Short-circuit output current 4/ 5/ CMOS Quiescent supply current 6/ 1, 2, 3 1,3 All All -200 200 50 100 150 mA µA 2 1 2 3 1 4 8 12 1,3 All 50 100 150 2 1 2 3 1 4 8 12 17 18 19 mA mA µA mA mA Quiescent supply current 6/ Input capacitance 7/ Output capacitance, CMOS 7/ Bidirect I/O capacitance, CMOS 7/ 4 4 4 All All All pF pF pF Notes: 1/ These devices are capable of being configured and support dual voltage: 3.3 V core/ 3.3 V and /or 5.0 V bus, 2.5 V core/3.3 V or 5.0 V bus, or 5 V core/5 V bus. The supply voltage range shall be specified in the AID. 2/ Devices supplied to this drawing will meet all levels M, D, P, L, R and F of irradiation. However, this device is only tested at the `R' or `F' level. Pre and Post irradiation values are identical unless otherwise specified in Table I. When performing post irradiation electrical measurements for any RHA level, TA = +25 C. 3/ Functional tests are conducted in accordance with MIL-STD-883 with the following input conditions: VIH = VIH(min) + 20%, - 0%; VIL ­ VIL(max) +0%, -50%, as specified herein for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 4/ Supplied as a design limit but not guaranteed or tested. 5/ Not more than one output may be shorted at a time for maximum duration of one second. 6/ All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low. 7/ Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1 MHz @ 0 V and a signal amplitude of 50 mV RMS STANDARD MICROCIRCUIT DRAWING
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SHEET B 11 Case X FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING
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SHEET 12 Case X - Continued CP1 CP2 CP3 CP4 VDDCQ VDDNCQ VDD1 VDD1 CP5 CP6 CP7 CP8 VDD1 VDD1 VDD1 VDD1 CP9 CP10 CP11 CP12 VDD1 VDD1 VDD1 VDDCQ Symbol A A1 A2 A3 A4 A5 A6 B1 B2 b c e F D1/E1 D2/E2 L L1 L2 K1 K2 K3 q1 J Millimeters Min Max 3.81 3.18 0.15 0.30 1.90 0.89 REF 0.89 1.27 REF 1.65 0.46 0.13 0.25 0.10 0.20 0.50 BSC 8.56 35.64 36.70 31.50 BSC 77.21 75.39 56.31 REF 1.52 2.54 3.56 70.00 REF 0.77 1.03 Inches Max .150 .125 .006 .012 .075 .035 REF .035 .050 REF .065 .018 .005 .010 .004 .008 .019 BSC .337 1.403 1.445 1.240 BSC 3.040 2.968 2.217 REF .060 .100 .140 2.756 REF .030 .040 Min Notes: 1. 2. 3. 4. 5. All exposes metalized areas are gold plated over nickel plating per MIL-PRF-38535. The lid is connected to VSS. Capacitors pads are designed for a MIL-PRF-55681 CDR33BX, 50V .1µF chip cap. Tiebar areas may have notches and tabs different than shown. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired areas. FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING
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SHEET C 13 Case Y FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING
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SHEET 14 Case Y - Continued CP1 CP2 CP3 CP4 VDD1 VDDCQ VDD1 VDD1 CP5 CP6 CP7 CP8 VDDCQ VDD1 VDD1 VDD1 CP9 CP10 CP11 CP12 VDD1 VDD1 VDDCQ VDD1 Symbol A A1 A2 A3 A4 A5 A6 B1 B2 b c e F D1/E1 D2/E2 L L1 L2 K1 K2 K3 K4 K5 q1 J R Millimeters Min Max 4.17 2.67 0.25 1.90 0.89 REF 0.89 1.27 REF 0.71 0.36 0.15 0.25 0.10 0.20 0.50 BSC 7.75 27.80 28.13 25.50 BSC 77.22 75.39 56.31 REF 1.40 1.65 2.79 2.22 1.40 65.89 REF 0.77 1.03 29.00 Inches Max .157 .105 .010 .074 .035 REF .035 .050 REF .028 .014 .005 .010 .004 .008 .020 BSC .306 1.097 1.107 1.004 BSC 3.040 2.968 2.217 REF .055 .064 .109 .087 .055 2.594 REF .030 .040 .787 Min Notes: 1. 2. 3. 4. 5. All exposes metalized areas are gold plated over nickel plating per MIL-PRF-38535. The lid is connected to VSS. Capacitors pads are designed for a MIL-PRF-55681 CDR33BX, 50V .1µF chip cap. Tiebar areas may have notches and tabs different than shown. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired areas. FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET B 15 TABLE IB. SEP test limits . Device Type TA = Temperature ±10°C 1/ 2/ Bias for latch-up test VCC = 5.5 V, SEU BIAS, VCC = 4.5 V, 3.0 V, or 2.25 V Effective LET no upsets [ MEV ­ cm /mg ]
2 Maximum device cross 2 section (µm ) (LET = 120) No latch-up LET 128 Mev ­ mg/cm2 All 3/ 4/ 4/ NOTE: Devices that contain cross coupled resistance must be tested at the maximum rated TA. 1/ For SEP test conditions, see 4.4.4.4 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. 3/ Worst case temperature for latch up test TA = +125°C; . worst case temperature for set up test TA = +25°C for SEU test. 4/ When characterized as a result of the procuring activities request, this parameter will be specified. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. Interim and final electrical test parameters shall be as specified in table II herein. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. b. c. STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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REVISION LEVEL 5962-04B01
SHEET B 16 TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. --1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 7 1, 7 Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q --1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 7 1, 7 Device class V --1, 2, 3, 7, 8, 9, 10, 11 2/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 7 1, 7 --- --- --- 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. b. Tests shall be as specified in table II herein. For device class Q and V, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device as described in the AID. Subgroup 4 (CIN, COUT, and CI/O measurements) shall be measured only for initial qualification and after process or design changes which may affect capacitance. Capacitance shall be measured between the designated terminal and GND. Capacitance testing shall be performed on three devices per Method 3012. A minimum of four pins per device shall be tested. Tested pins shall be selected based on engineering analysis of the package interconnect drawing to determine which pins will have the highest capacitance. The sample sizes may be increased based on engineering judgement, but shall not be decreased. c. STANDARD MICROCIRCUIT DRAWING
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SHEET 17 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883. TA = +125°C, minimum. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. b. c. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point electrical parameters shall be as specified in table IIA herein. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019. 4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level greater than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table I. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.5 Single event phenomena (SEP). SEP testing shall be required on class V devices (See 1.5). SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. The recommended test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° angle 60° ). No shadowing of the ion beam due to fixturing or package related effects is allowed. b. The fluence shall be 100 errors or 106 ions/cm2. c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The test temperature shall be as specified in Table IB SEP test limits. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET C 18 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Additional information. manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of transients (SEP). e. Occurrence of latchup (SEP). A copy of the following additional data shall be maintained and available from the device STANDARD MICROCIRCUIT DRAWING
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REVISION LEVEL 5962-04B01
SHEET 19 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 07-02-26 Approved sources of supply for SMD 5962-04B01 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ 2/ 5962-04B0101Q_C 5962F04B0101V_C 5962-04B0102Q_C 5962F04B0102V_C 5962-04B0103Q_C 5962F04B0103V_C 5962-04B0104Q_C 5962F04B0104V_C 5962-04B0105Q_C 5962R04B0105V_C 5962-04B0106Q_C 5962R04B0106V_C 5962-04B0107Q_C 5962R04B0107V_C 5962-04B0108Q_C 5962R04B0108V_C 5962-04B0109Q_C 5962R04B0109V_C 5962-04B0110Q_C 5962R04B0110V_C 5962-04B0111Q_C 5962R04B0111V_C 5962-04B0112Q_C 5962R04B0112V_C 5962-04B0113Q_C 5962R04B0113V_C 5962-04B0114Q_C 5962R04B0114V_C 5962-04B0115Q_C 5962R04B0115V_C 1/ Vendor CAGE number 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 65342 Vendor Similar PIN 3/ UT06MRA010 UT06MRA025 UT06MRA050 UT06MRA075 UT06MRA100 UT06MRA150 UT06MRA200 UT06MRA250 UT06MRA300 UT06MRA350 UT06MRA400 UT06MRA450 UT06MRA500 UT06MRA550 UT06MRA600 2/ 3/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. Due to the nature of this SMD, the standard microcircuit drawing PIN and corresponding vendor similar PIN shall be specified in the AID. The vendor similar PIN will be based on the UT06MRA gate array family. Contact the listed approved source of supply for availability of case outlines (defined in 1.2.4) for each device. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 65342 Vendor name and address Aeroflex Colorado Springs Inc. 4350 Centennial Boulevard Colorado Springs, CO 80907 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.