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DEI 1028 Voltage Clamping Circuit Page 1 of 5

© 2002 Device Engineering Inc.
DS-MP-01028 Rev. C
9/19/2002
Features
Protection for power electronics on 28VDC avionics or industrial power bus. Controls power P-FET to clamp transient at 34V. Small foot print (8L SOIC NB). Wide input voltage range. Programmable Undervoltage Lockout. Logic compatible On/Off input. Stable over temperature. Soft start delay.

DEI 1028
Voltage Clamping
Circuit
Device
Engineering
Incorporated
General Description
The DEI1028 is a control circuit for a 28VDC power bus voltage clamp. It is designed for use as the front end to
a 28VDC input power supply to provide transient voltage protection. It controls the gate drive of a P-Channel
power MOSFET to linearly clamp the output during over voltage transients. The output voltage is maintained
below the clamping threshold of 35V (max) which is adequate to protect most Commercial-Off-The-Shelf
switching supplies, linear regulators, and op amps. The device protects against a 100V spike of 100ms duration
and provides overshoot protection.

There is an Undervoltage Lockout feature that shuts the Power MOSFET off when the input voltage is below a
user programmed threshold. An open collector logic output annunciates the under voltage status. There is also a
logic on/off input which may be used to control the power circuit. An external capacitor may be used to set a delay
from when input power is applied to when the MOSFET is turned on.
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
Pin #
Name
Type / Description
1
GATE
OUTPUT. Controls the gate of the external p-channel power MOS-
FET.
2
CAP
IN/OUT. Controls the soft start delay of the device. Use 0.22uF for
200ms minimum soft start time.
3
IN
INPUT. Power input for the DEI1028 Voltage Clamp.
4
UVL
INPUT. Controls the under voltage lockout condition of the device.
5
NON
INPUT. Logic low enables device. Logic high disables device.
6
NUV
OUTPUT. Open collector output. Active low when IN is below UVL
threshold.
7
GND
POWER. Ground
8
OUT
INPUT. Feedback to gate control from drain of Power MOSFET.
Table 1: Pin Definitions
DEI1028 Pin Diagram
8
7
6
5
2
3
4
1
GATE
CAP
IN
UVL
OUT
GND
NUV
NON Page 2 of 5

© 2002 Device Engineering Inc.
DS-MP-01028 Rev. C
9/19/2002
Table 2: Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
IN Pin: Relative to GND
Continuous
1 mS Transient
100 mS Transient
V
IN


0 to +40
-50
+100

V
V
V
OUT Pin: Relative to GND
V
OUT

-0.5 to + 40

V
Operating Temperature
T
A

-55 to +85
o
C
Storage Temperature
T
STG

-55 to +125
o
C
Lead soldering temperature (10 sec duration)

+280
o
C
UVL Pin: Relative to V
IN

V
UVL

-6 to +0.5
V
CAP Pin: Relative to V
IN

V
CAP

-20 to +20

V
GATE Pin: Relative to V
IN

V
GATE

-10 to +0.5

V
NON Pin: Relative to GND
V
NON

-0.5 to + 6.0
V
NUV Pin: Relative to GND
V
NUV

-0.5 to + 20

V
Table 3: Operating Characteristics (Ta = -55 ºC to 85 ºC)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Clamp output voltage
V
O(CL1)

V
IN
= 40 V, 60V
33

35
V
Clamp output voltage
V
O(CL2)

V
IN
= 100 V
(1)

33

35
V
Clamp output voltage
Vo
(CL3)

V
IN
= -50 V
(1,2)

-
-
-

Source-Gate FET voltage (ON)
V
SG(1)

RUVL = 13.6 k, VIN = 14 V
9

10
V
Source-Gate FET voltage (OFF)
V
SG(2)

RUVL = 13.6 k, VIN = 10 V
0

0.7
V
Source-Gate FET voltage (ON)
V
SG(1)

RUVL = 7 k, VIN = 25 V
9

10
V
Source-Gate FET voltage (OFF)
V
SG(2)

RUVL = 7 k, VIN = 19.5 V
0

0.7
V
Source-Gate FET voltage (LINEAR)
V
SG(3)

35V < V
IN
< 100V,
VOUT= Clamp Voltage (3335v)
0.7

9
V
Turn-on time
t
ON

C = 0.22
µF; see Figures 4, 5.
200


msec
Soft start delay charge current
I
ST

V
IN
> 10V
0.75

3
µA
Soft start delay threshold
V
ST

V
IN
> 10V
V
IN
- 2.5

V
IN
- 2.9
V
Output overshoot voltage
Vo
MX

See Figure 6.
(1)


35
V
Output settling time
t
S

See Figure 6.
(1)



2
msec
Supply Current
I
IN

V
IN
= 30 V


5
mA
Notes:
1.
Guaranteed by design and not production tested.
2.
Device must survive this test. Duration of negative voltage must be limited to less than 1 ms due to heating effects.
3.
MOSFET capacitance (Cgs) must be in the range 500 ~ 5000 pF. If below 500 pF, an external 470 pF capacitor must be connected
between the DEI1028 OUT and GATE pins.
Table 4: Logic Characteristics (Ta = -55 ºC to 85 ºC)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
NON input logic 1 level
V
IH

V
IN
= 8 to 30 V
2.8


V
NON input logic 0 level
V
IL

V
IN
= 8 to 30 V


0.8
V
NON input logic 0 current
I
IL

V
NON
= 0 V
V
IN
= 8 to 30 V
-300

-30
µA
NUV output logic 1 level
V
OH

R
UVL
= 13.6 k, V
IN
= 14 V,
R
PU
= 10 kto 5V (See Figure 7.)
V
NUV output logic 0 level
V
OL

R
UVL
= 13.6 k, V
IN
= 10 V
I
OL
= 420 µA (See Figure 7.)


0.8
V
4.75
Page 3 of 5

© 2002 Device Engineering Inc.
DS-MP-01028 Rev. C
9/19/2002
Table 4: Under voltage Lockout Threshold
R
UVL

TEMP
SYMBOL
MIN
TYP
MAX
UNITS
13.6K 85
ºC V
IN
12.0 - 14.0 V
13.6K 25
ºC V
IN
11.0 - 13.0 V
13.6K -55
ºC V
IN
10.0 - 12.0 V
7K 85
ºC V
IN
22.0 - 24.0 V
7K 25
ºC V
IN
21.0 - 23.0 V
7K -55
ºC V
IN
19.5 - 21.5 V
Undervoltage Lockout
An Undervoltage Lockout feature is provided to prevent large currents from flowing through the MOSFET if the
input voltage is too low. The resistor is placed between the IN and UVL pins. The following formula is used to
determine the resistor value to set the nominal (25 ºC) lockout threshold voltage:
(see figures 6 & 7 for temperature characteristics)
R
UVL =
(100k
)
1.45
(V
UVL
1.45)
Gate Drive

The DEI1028 device is designed to control the gate of a P-Channel power MOSFET such as the IRF9540. At
normal operation the gate output turns the transistor ON to saturation. Below under voltage conditions the
MOSFET is shut off. In clamp mode the MOSFET is driven to linear mode, keeping the output at approximately
34 V.
Figure 1: Typical Application
Soft Start Delay

An external capacitor between CAP and the input voltage may be used to set a turn on delay time. See figure 4.

T
ON
(mS)
C
ss
(nF)

At start up, the voltage across the capacitor is approximately zero, the voltage at the CAP pin is approximately
the input voltage, and the MOSFET is turned off. The 1028 CAP pin provides a current sink (approx. 2uA) to
charge the capacitor. The 1028 turns the MOSFET on when the voltage across the capacitor reaches
approximately 2.7V. Page 4 of 5

© 2002 Device Engineering Inc.
DS-MP-01028 Rev. C
9/19/2002
t
ON
30V
40V
Input
Output
Figure 4. Turn On Time
4.5V
25V
0
NON
Output
t
ON
Figure 5. Logic Control (NON pin)
Figure 6. Overshoot and Settling
Figure 7. Undervoltage Logic Output
40V
25V
V
OMX
2ms
1%
t
s
Input
Output
2ms
10K
+5V
DEI1028
V
NUV
NUV
Reference Voltage vs Temperature
1.47
1.57
1.65
1.345
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
-100
-50
0
50
100
150
Temp (C)
Re
f
e
r
e
nc
e
Volt
a
g
e
(
V
)
.
UVL Cutoff vs Temperature
13.1
13.7
11.21
12.5
22.8
24.1
25.41
20.58
0
5
10
15
20
25
30
-100
-50
0
50
100
150
Temp (C)
UVL Volt
age (
V
)
13.6K
7K
Figure 2:
Typical UVL cutoff voltage by temperature for Ruvl = 7K
and Ruvl = 13.6K
Figure 3:
Typical UVL Reference Voltage vs. Temperature. Page 5 of 5

© 2002 Device Engineering Inc.
DS-MP-01028 Rev. C
9/19/2002
Figure 8: 8 Lead SOIC Outline Drawing

Moisture Sensitivity: JEDEC J-STD-020A MSL 1
Part Number
Marking
Package
Temp
DEI1028SES
DEI1028
8-lead SOIC
-55 / +85 °C
Table 8: Ordering Information
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
Theta
jc
Junction
to
Case 40 °C/W
Theta
ja

Junction to Ambient
4 layer board
135 °C/W
T
j-MAX

Max Junction Temperature
125
°C
Table 7: 8 LD SOIC Thermal Characteristics
Package Characteristics
: