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High Current Low Voltage Solution For Microprocessor Applications from 48V Input High Current, Low Voltage Solution For Microprocessor
Applications from 48V Input
Paul A. Yeaman, Vicor VI Chip, USA


Abstract
A novel approach for providing microprocessor power directly from 48V is proposed. This solution
enables high voltage, low current to be distributed throughout a system, minimizing distribution losses,
while providing low voltage, high current direct from the 48V input in the most efficient manner
possible. This solution is also extremely small, minimizing the required footprint at the microprocessor
core, and extremely fast, eliminating the need for capacitors at the point of load.

1.0 Background
Evolving CMOS technology has been continuing
to drive the core voltage of microprocessors
down and the core currents of microprocessors
up [1]. As the core voltage decreases and the
current increases, the challenges for providing
this power have been steadily mounting. Higher
current results in exponentially higher dissipative
losses both in synchronous MOSFETs and in
copper distribution paths. Lower output voltages
make the following equation impractical:
D
V
V =
2
V
Q
F
IN
OUT


[Eq.
1]
V
OUT
is the Output (Microprocessor Core)
voltage, VIN is the Input (Source) voltage and D
is the duty cycle. In response to a smaller value
of VOUT, D must also become smaller. This
impacts the ratio of switching and core losses to
dissipative losses in MOSFETs and magnetics. A
lower source voltage could be considered to
enable D to remain constant, however overall
system efficiency would be impacted by the
following relationship:
dist
S
in
LOSS
R
I
P
_ =


[Eq.
2]
P
where P
LOSS
is the power lost in the input
distribution traces, I
IN
is the input current to the
converter, and R
S_DIST
is the impedance of the
input current distribution path (including copper
traces and connectors). Decreasing the input
voltage to keep D constant would increase Iin
linearly. This would increase P
LOSS
as a function
of the square of I
IN
, negatively impacting overall
system efficiency.
A second evolving requirement for
microprocessor power is small size. As CMOS
fabrication capabilities continue to evolve it
becomes possible to include more transistors on
a die, and hence more functionality within a
microprocessor chip. By the same token, the
increased functionality applies to the
motherboard as well, as increasingly complex
microprocessors require increased memory, and
peripheral devices (bus controllers, graphics
processors, co-processors). The increasing
device density leaves little room for the requisite
power conversion and necessitates that the
power conversion must not only cope with higher
current output, but be smaller [2].
The key to small size for power conversion has
long been in high switching frequency. A high
switching frequency enables smaller magnetics,
the largest component in typical power
conversion systems by volume. Unfortunately
there has long been a point of diminishing
returns driven by the following equation:
g
g
sw
loss
SW
=
1
_


[Eq. 3]
where F
SW
is the switching frequency, Q
G
is the
gate charge of the switching MOSFETs and V
G
is
the Gate voltage of the switching waveform. As
the switching frequency increases, the switching
losses increase as well, requiring a MOSFET
with lower gate charge, or lower gate threshold.
Such devices typically come with the penalty of a
higher R
dson
, thus increasing dissipative losses. A second loss component that is directly
proportional to switching frequency is described
below [3]:
sw
sw
sw
off
sw
sw
sw
on
sw
SWloss
f
V
I
T
V
I
T
P +
=
)]
(
2
1
)
(
2
[
_
_
2
1

[Eq. 4]
In the equation above, T
sw_on
and T
sw_off
are the
turn on and turn off times of the MOSFET, I
sw
is
the peak current through the MOSFET, V
sw
is the
voltage across the MOSFET when off and fsw is
the switching frequency. Since the MOSFET
does not instantaneously turn on or off, there are
brief periods where the device will be dissipating
power while transitioning off or on. The amount
of power dissipated during these periods
increases linearly with frequency.
2.0 Input Voltage Independent
Solution with High Switching
Frequency
The problems outlined above call for a solution
with the following attributes:
1) High switching frequency to enable small
size.
2) Decoupling of duty cycle from input and
output voltage (as described in Eq. 1).
One added requirement that is imposed for the
sake of pragmatism requires that any proposed
system contain no additional penalties in terms
of further power losses (contributing to overall
inefficiency) or compromises that would affect
the performance of the microprocessor load.
The proposed solution consists of a Sine
Amplitude Converter (SAC, Figure 1) at the
point of load (microprocessor) powered by a ZVS
Buck-Boost regulator (Figure 7) from the 48V
input. Both solutions with the external feedback
and control loop are shown in Figure 9.
3.0 Sine Amplitude Converter
Point of load Conversion
The SAC uses a high frequency resonant tank to
move energy from input to output [4]. The
resonant tank is formed by C
res
(shown in Figure
1) and leakage inductance in the power
transformer windings (designated P in the
schematic). The four MOSFETs in the H-bridge
are alternately switched at the resonant
frequency of the tank. The presence of load
current (+OUT to OUT) creates resonant
current through the tank, which is rectified by the
two secondary switches and filtered by the
output capacitance.
The SAC can be functionally distilled into the
behavioral model shown in Figure 2. In this
representation, several relationships become
apparent.

Figure 2: Behavioral Model of SAC [5]
At no load:
K
V
V
IN
OUT =

[Eq.
5]
K represents the turns ratio of the SAC.
Rearranging Equation 5:
IN
out
V
K
= V
R
I
K
V
V


[Eq.
6]
In the presence of load, V
OUT
is represented by:
OUT
OUT
IN
OUT =

[Eq. 7]
and I
OUT
is represented by:
K
I
Q
IN
OUT
I
I =

[Eq.
8]
SAC
Control
P
P
P
D
D
D
D
D
+IN
-IN
+OUT
-OUT
D
P=Power Transformer
D=Drive Transformer
Cres
D
Figure 1: Sine Amplitude Converter R
OUT
represents the impedance of the SAC, and
is a function of the R
dson
of the input MOSFETs
and the winding resistance of the Power
transformer. By a similar token, I
Q
represents the
quiescent current of the SAC control and gate
drive circuitry shown in Figure 1.
In a transformer based topology, V
OUT
is a
function of V
IN
, not D. K is a constant and in
order to provide a lower V
OUT
, the Vin must be
lowered. It should also be noted that K as a
value can be very small. Unlike the Duty Cycle
limitation where the functional limitation is in the
ability to switch a MOSFET, K enables input to
output ratios as large as 32:1 or greater.
The use of DC voltage transformation provides
some additional interesting attributes. Assuming
for the moment that R
OUT
and IQ =0, equation 7
now becomes equation 6 and is essentially load
independent. A resistor R
IN
is now placed in
series with V
IN
as shown in Figure 3.

The relationship between V
IN
and V
OUT
becomes:
K
R
I
V
V =
)
(
2
IN
IN
OUT


[Eq. 9]
Substituting the simplified version of Equation 8
(I
Q
is assumed = 0) into Eq. 9 yields:
K
R
I
K
V
V
OUT
IN
OUT
=

[Eq. 10]
This is similar in form to Eq. 7, where R
OUT
is
used to represent the characteristic impedance
of the SAC. However, in this case a real R on the
input side of the SAC is effectively scaled by K
2

with respect to the output.
There are several implications in the context of
powering a microprocessor. Consider the SAC
depicted in Figure 3. Assuming that R = 1 , the
effective R as seen from the secondary side is
.98m . A 1 upstream series input impedance
essentially looks like 1m .
A similar exercise should be performed with the
addition of a capacitor, or shunt impedance, at
the input to the SAC. A switch in series with V
IN

is added to the circuit. This is depicted in Figure
4.

A change in V
IN
with the switch closed would
result in a change in capacitor current according
to the following well known equation:
dt
C
t
I
IN
c
=
)
(
dV
K
I
I

[Eq.
11]
Assume that with the capacitor charged to V
IN
,
the switch is opened and the capacitor is
discharged through the idealized SAC. In this
case,
OUT
c =

[Eq.
12]
Substituting Equations 5 and 12 into Eq. 11
reveals:
dt
dV
K
C
I
OUT
OUT =
2

[Eq.
13]
Once again, writing the equation in terms of the
output has yielded a K
2
scaling factor for C, this
time in the denominator of the equation.
Again, the implications for a low voltage, high
current microprocessor application are worth
considering. For a K factor less than unity, as
shown in Figure 4, this results in an effectively
larger capacitance on the output when
expressed in terms of the input. With a K=1/32
as shown in Figure 4, C=1uF would effectively
appear as C=1024uF when viewed from the
output.
Low impedance is a key requirement for
powering a high current, low voltage load
efficiently. A switching regulation stage should
have minimal impedance, while simultaneously
providing appropriate filtering for any switched
Figure 4: Sine