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A Scalable SiC Device for DC/DC Converters in Future Hybrid Electric Vehicles
1
A Scalable SiC Device for DC/DC Converters in
Future Hybrid Electric Vehicles

Robin Kelley
1
, Michael S. Mazzola
1
, and Volodymyr Bondarenko
2

1
SemiSouth Laboratories, Inc., 200 Research Blvd., Starkville, MS 39759
2
Center for Advance Vehicular Systems (CAVS),
Mississippi State University, 201 Research Blvd., Starkville, MS 39759



Abstract The potential increased power density and high
temperature capability of silicon carbide makes it an ideal
candidate for use in future hybrid electric vehicle (HEV)
technology. A secondary cooling system is required to maintain
an 85
o
C base plate temperature for silicon based power electronics;
but by creating a silicon carbide (SiC) based replacement this
requirement could be relaxed. One anticipated benefit, among
many, is that the secondary cooling loop could be eliminated and
instead interfaced with the engine coolant system designed to
maintain a maximum temperature of 105
o
C. The purpose of this
paper is to present an all-SiC scaled prototype that is modeled after
the DC-DC converter used in the Prius II to establish a high
voltage DC bus interconnecting the motor and generator. The
design uses a SiC JFET and SiC Schottky diode as the switching
pair of a 1 kW scale model that investigates an inherently safe
approach for use in future HEVs. The ability to parallel these
unipolar devices results in a scalable device technology capable of
achieving high-current, 600-V SiC switch technology in the near
term that offers a potential 100
o
C increase in junction temperature
above that rated for comparable silicon IGBTs.
I.

I
NTRODUCTION

This work is motivated by an industry wide interest to
integrate SiC power devices in future automotive
applications. The need to mount electric motor drives and
other power converter electronics under the hood and as
close to the motor as possible demands that the power
electronics installed must either be capable of enduring the
high under-hood temperatures or incorporate an extra
cooling system. The use of SiC power device in under-
hood power electronics would allow for more relaxed
cooling requirements, elimination of a second cooling
system, and integration with the current motor coolant
system. The ability to reduce the necessary cooling
mechanisms and overall package design is what will
balance out the higher cost of using SiC devices over silicon
in future automotive electronics.

Fig. 1 provides a block diagram of the high voltage
system used in the current Toyoto Prius HEV. Within the
Prius a 200V battery bank is established by connecting
several individual batteries in series. In the first generation
vehicles, original Prius, this 200V battery voltage was used
to directly drive the electric motor. In the second
generation vehicles, Pruis II, a high voltage power converter
was included to boost this voltage to create a 500-V bus
voltage for the motor/generator. While the power
electronics in a modern hard HEV power train, such as
the system in the Toyota Prius II, is typically rated for 50
kW, a scaled prototype was designed and fabricated to
investigate gate driver design to provide initial results that
show the feasibility of SiC in HEV power electronics.

Fig. 1.

Block diagram of the high voltage system in the
Toyota Pruis
II.

C
ONVERTER
D
ESIGN AND
R
ESULTS

A classic boost converter was designed to deliver roughly
1 kW of continuous power, operating at 100 kHz, and using
SiC devices as the switching pair. This prototype boosts an
input voltage of 200 V simulating minimum battery bank
voltage to an output voltage of 500 V, the regulated DC bus
voltage within the Prius II [1]. Even though the JFET is
generally thought of as a normally on device, SiC JFETs
can be fabricated and practical gate drivers designed to
support JFETs with less negative, or even positive,
threshold voltage. Such devices can exhibit an ideal
combination of enhancement mode functionality, similar to
conventional normally off silicon devices, with the
advantage of bias-enhanced blocking voltage unique to the
JFET that permits higher blocking voltage and lower on-
resistance [2].

In a conventional boost converter, as well as
many types of resonant converters, enhancement mode
functionality and bias-enhanced blocking greatly simplifies
the gate driver and start up circuit design such that SiC
JFET converter has essentially the same safety as a
converter switched with a purely normally off silicon
switch. This is because many converters, including the
boost converter considered here, stress the switch at two
different characteristic voltage levels: a static or dc voltage
level, and a higher dynamic voltage level. If the SiC JFET is
2
rated to block the lower dc value at V
GS
= 0 V, and the gate
driver is designed to supply the small negative gate-source
bias voltage (say V
GS

-3 V) necessary for the JFET to
block the higher dynamic voltage, an inherently safe design
results because the higher dynamic voltage can only exist if
the converter, including gate-drive circuitry, is working
properly. Typically, the enhancement-mode JFET can block
50% of rated voltage (
300 V) at V
GS
= 0 V, and 100% of
rated voltage (600 V) with V
GS

-3 V. Fig. 2 provides
evidence of the enhancement mode blocking capabilities in
a typical BV
DS
vs V
GS
curve.

Fig. 2.

BV
DS
vs V
GS
curve for Bias Enhanced SiC
JFET.

Fig. 3.

HEV boost converter solution made with a SiC
JFET and SiC SBD.


Fig. 4.

Gate driver using standard ASIC controller.

The core boost converter, as shown in Fig. 3, was
designed according to standard approaches found in the
literature [3]. The circuit shown in Fig. 4 is an effective
solution for interfacing a SiC JFET with a standard
commercially available ASIC controller. Voltage V
_
is a
low-voltage rail derived from an auxiliary winding on the
boost inductor; thus dynamic charging of the output
capacitor, the source of the dynamic voltage stress on the
JFET while the freewheeling diode is conducting, must also
charge the capacitor supporting the V
_
voltage bus. Since
the output of the ASIC typically varies between GND and
V
CC
, a totem pole is used to level shift the output control
pulse to provide the dynamic gate-source voltage pulse
ranging between V
GS
+3 V (necessary for turn-on), and
V
GS
V- (necessary to block the dynamic voltage stress
while the freewheeling diode is conducting). The JFET
requires minimal gate-drive current; therefore, the ASIC is
capable of sourcing and sinking the typical gate currents
needed to drive a modest number of SiC JFETs in parallel.
Thus, Fig. 4 incorporates the use of a bypass diode D in
place of the high-side NPN transistor otherwise found in the
typical totem-pole output buffer. In a fully scaled SiC
switch rated in the several hundreds of amperes and
consisting of a large number of paralleled JFET die, a
higher gate current may be required, in which case the
bypass diode is replaced with a high-side NPN transistor
supplied by V
+
, a positive rail voltage equal to the +3 V
required for turn on.
The results for the prototyped boost converter operating
at 1 kW are shown in Fig. 5. Again the prototype was
modeled after the boosting requirements of the high voltage
power converter required in the high voltage system for the
Toyota Prius II as shown in Fig. 1. The prototype
successfully boosted a 200 VDC input to establish a
regulated 500 VDC voltage bus while maintaining a total
output power of 1 kW, and operating at > 90% efficiency.
Fig. 5 provides an oscilloscope capture of the critical
waveforms for the boost converter, V
IN
, V
DS
, V
GS
, and I
L
.
Fig. 6 provides a zoomed view of the drain-source voltage,
gate-source voltage, and boost inductor current in order to
illustrate the excellent switching characteristics of the SiC
power devices and the gate driver circuit which aids to
further reduce switching losses by providing a very fast
switching drive signal. The 100 kHz switching frequency is
no challenge for the SiC switching pair, JFET and Schottky
barrier diode. This figure also illustrates the two levels of
voltage stress that the switch must be able to withstand
(static stress: V
in
= 200 V DC, dynamic stress: V
DS(peak)
=
V
out
= 510 V).
This is an excellent application for the bias-enhanced SiC
JFET presented in previous work [2] and revisited at the
beginning of this section, Fig. 2. By using a bias-enhanced
SiC JFET, inherently safe operation is provided in the case
of a gate driver by the characteristic enhancement mode
functionality of this particular device. At start-up and
during any driver failure event the switch is capable of
blocking the full DC input voltage indefinitely as if it were
any other normally off device. Once switching is initiated a
3
negative bias is derived to allow the sw