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Power Optimization of Variable Voltage Core-Based Systems
Power Optimization of Variable Voltage Core-Based Systems
Inki Hong
y
, Darko Kirovski
y
, Gang Qu
y
, Miodrag Potkonjak
y
, and Mani B. Srivastava
z
y
Computer Science Department, University of California, Los Angeles, CA 90095-1596 USA
z
Electrical Engineering Department, University of California, Los Angeles, CA 90095-1596 USA
Abstract
The growing class of portable systems, such as personal computing
and communication devices, has resulted in a new set of system de-
sign requirements, mainly characterized by dominant importance
of power minimization and design reuse. We develop the design
methodology for the low power core-based real-time system-on-
chip based on dynamically variable voltage hardware. The key
challenge is to develop effective scheduling techniques that treat
voltage as a variable to be determined, in addition to the conven-
tional task scheduling and allocation. Our synthesis technique also
addresses the selection of the processor core and the determination
of the instruction and data cache size and conguration so as to
fully exploit dynamically variable voltage hardware, which result
in signicantly lower power consumption for a set of target ap-
plications than existing techniques. The highlight of the proposed
approach is the non-preemptive scheduling heuristic which results
in solutions very close to optimal ones for many test cases. The ef-
fectiveness of the approach is demonstrated on a variety of modern
industrial-strength multimedia and communication applications.
1
Introduction
1.1
Motivation
The growing class of portable systems, such as personal comput-
ing and communication devices, demands data- and computation-
intensive functionalities with low power consumption. For such
systems, power consumption is the primary design goal since the
battery life is a primary constraint on power, due to the fact that
the battery technology has not followed the progress pace of the
semiconductor industry. Recent advances in power supply tech-
nology along with custom and commercial CMOS chips that are
capable of operating reliably over a range of supply voltages make
it possible to create processor cores with supply voltage that can be
varied at run time according to application timing constraints. The
variable voltage processor core can be made to operate at different
optimal points along its power vs. speed curve in order to achieve
much higher energy efciency than existing techniques for a wider
class of applications. Such systems also require design exibil-
ity which result in the need for implementation on programmable
processor platform. In fact, embedded software running on RISC
and DSP processor cores has emerged as a leading implementa-
tion methodology for such applications as speech coding, modem
functionality, video compression and communication protocol pro-
cessing [15]. Current semiconductor technology allows the inte-
gration of programmable processors and memory structures on a
single die, which enables the implementation of a system on a sin-
gle chip. Similarly, the exponential growth of both applications and
implementation technology has outpaced the design productivity of
the traditional synthesis process. The shrinked time-to-market win-
dow has exacerbated the situation. There is a wide consensus that
only through reuse of highly optimized cores the demands of the
pending applications and the potential ultra large scale integration
may be matched. Therefore, low power core-based system-on-chip,
consisting of a variable voltage programmable processor core and a
memory hierarchy, attracted much attention of virtually all silicon
vendors.
Microprocessor
core
I-Cache
D-Cache
Memory Management
Unit, Cache
Controller, I/O
Hardware
Accelerators,
Interface, ...
I/O
Internal Bus
Optimization Target
Figure 1: A typical core-based application-specic system-on-chip.
Our synthesis technique targets typical modern application spe-
cic system-on-chip, consisting of a variable voltage processor core,
instruction and data cache, and a number of optional hardware ac-
celerators and control blocks as depicted in Figure 1. The distribu-
tion of power dissipation by the components of application-specic
system-on-chip depends on the actual applications running on the
system. However, extensive studies indicate that the power con-
sumption of the processor and cache cores accounts for signicant
portion of the overall power consumption of the described system-
on-chip [6]. Therefore, in this paper we focus on the power opti-
mization of the processor and cache cores.
The most effective way to reduce power consumption of a pro-
cessor core in CMOS technology is to lower the supply voltage
level, which exploits the quadratic dependence of power on voltage
[2]. Reducing the supply voltage however increases circuit delay
and decreases clock speed. The resulting processor core consumes
lower average power while meeting the deadlines. This technique
is ineffective when tight deadlines are present in systems. An-
other power optimization technique for processor cores is the sys-
tem shutdown [15]. The system shutdown technique, though usable
even in the presence of tight deadlines, is inferior to the supply volt-
age reduction technique for the cases when both techniques can be
applied. The limitations of the techniques arise due to the fact that
systems are designed with a xed supply voltage. The supply volt-
age reduction technique attempts to nd a single optimal voltage
level for the entire processor operation, while the system shutdown
technique makes a binary runtime decision whether to turn on or
off the power supply.
The goal of the research presented in the paper is to develop
the design methodology for the low power core-based real-time
system-on-chip based on dynamically variable voltage hardware.
The key challenge is to develop effective scheduling techniques that
treat voltage as a variable to be determined, in addition to the con-
ventional task scheduling and allocation. Our synthesis technique
also addresses the selection of the processor core and the determi-
nation of the instruction and data cache size and conguration so as
to fully exploit dynamically variable voltage hardware, which will result in signicantly lower power consumption for a set of target
applications than existing techniques.
1.2
Motivational Example
To illustrate the key point of the proposed dynamically variable
voltage approach, we consider a set of tasks as a motivational ex-
ample, shown in Table 1. Two independent computations
Task
A
and
Task
B
need to be executed on an embedded processor core in
the time interval [0, 20]. Each task can be executed immediately
after its arrival and is required to be nished by its deadline time.
Preemption is not allowed due to the high context-switching cost.
task
arrival
deadline
execution time at 3.3 V
A
0
6
5
B
3
20
5
Table 1: The characteristics of the 2 tasks used to illustrate the
motivation for dynamically variable voltage approach.
Assume the maximum supply voltage to be

V
dd

r
ef
=
3
:
3
volts. Power is normalized to its value at the reference point, i.e.,
P
3
:
3
volts

=
1
Watt. Reducing supply voltage results in in-
creased circuit delay and to a good accuracy, the circuit delay is
given by
k

V
dd
V
dd
,V
t

2
, where
V
t
is the threshold voltage, and
k
is a
constant [2]. We assume a typical value of
0
:
8
volts
for the thresh-
old voltage. The power consumption is given by
P
=
C
L
V
2
dd
f
,
where
f
is the system clock frequency,
V
dd
is the supply voltage,
C
L
is the load capacitance and
is the switching activity [2]. We
now consider the application of shutdown, supply voltage reduc-
tion, both shutdown and supply voltage reduction, and dynamically
variable voltage approach, respectively.
With the shutdown technique, the system will operate at
V
dd
=
3
:
3
volts. The
Task
A
is executed in the interval [0, 5]. The
Task
B
is executed in the interval [5,10]. The processor can be shut down
for the interval [10, 20] and then be resumed for the next task. The
duty cycle of the processor is 50 %, so the average power consump-
tion is
0
:
5
Watts.
With the supply voltage reduction technique, the system will
operate at a lower but xed supply voltage. The tight deadline
on
Task
A
means that supply voltage can not be lowered less than
V
dd
=
2
:
97
volts. Thus, the system operates at
V
dd
=
2
:
97
volts
with
P
2
:
97
volts

=
0
:
67
Watts.
Task
A
is executed in the inter-
val [0, 6].
Task
B
is executed in the interval [6,12]. The average
power consumption is
0
:
67
Watts. Since the system can be shut
down during the interval [12, 20], the average power consumption
can be lowered to
0
:
67

12
20
=
0
:
40
Watts, which results in 20 %
power reduction, compared to the shutdown technique.
With the variable voltage hardware, one can schedule the two
tasks such that