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Low-Voltage Low-Power LVDS Drivers
472
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005
Low-Voltage Low-Power LVDS Drivers
Mingdeng Chen, Member, IEEE, Jose Silva-Martinez, Senior Member, IEEE, Michael Nix, and
Moises E. Robinson, Member, IEEE
AbstractTwo low-voltage low-power LVDS drivers used for
high-speed point-to-point links are discussed. While the previously
reported LVDS drivers cannot operate with low-voltage supplies,
the proposed double current sources (DCS) LVDS driver and the
switchable current sources (SCS) LVDS driver are suitable for
low-voltage applications. Although static current consumption is
greater than the minimum amount required by the signal swing,
the DCS LVDS driver is simple and fast. The SCS LVDS driver, by
dynamically switching the current sources, draws minimum static
current and reduces the power consumption by 60% compared to
previously reported realizations. Both drivers were fabricated in a
standard 0.35- m CMOS process; they are compliant with LVDS
standards and can operate at data rates up to gigabits-per-second.
Index TermsBack-plane drivers, fast data communication cir-
cuits, input/output (I/O) drivers, low-voltage differential signaling
(LVDS), low-voltage low-power integrated circuits.
I. I
NTRODUCTION
T
HE ever-increasing processing speed of microprocessor
motherboards, optical transmission links, chip-to-chip
communications, etc., is pushing the off-chip data rate into
the gigabits-per-second range. While scaled CMOS technolo-
gies continue to enhance on-chip operating speeds, off-chip
data rates have gained little benet from the increased silicon
integration. This is primarily due to the excessive power con-
sumption necessary for driving impedance-controlled electrical
interconnects, which leads to an increase in costs related to
packaging and thermal management [1]. In the past, off-chip
high data rates were achieved by massive parallelism, with
the disadvantages of increased complexity and cost for the
IC package and the printed circuit board (PCB). Therefore,
it is benecial to move the off-chip data rate to the range of
Gb/s-per-pin or above. Reducing the power consumption is also
critical for battery-powered portable systems as well as some
other systems in order to extend the battery life and reduce the
costs related to packaging and additional cooling systems.
Scalable Coherent Interface (SCI) is a high-speed packet
transmission protocol that efciently provides the functionality
of bus-like transactions (read, write, lock, etc.), but it uses a col-
lection of fast point-to-point links instead of physical buses to
reach higher speeds. The initial physical implementations were
based on emitter coupled logic (ECL) signal levels [2], which
consume more power than is practical in a low-cost workstation
environment. Low-voltage differential signaling (LVDS) is a
Manuscript received March 2, 2004; revised August 24, 2004.
M. Chen and J. Silva-Martinez are with Texas A&M University, Analog
and Mixed-Signal Center, College Station, TX 77843-3128 USA (e-mail:
jsilva@ee.tamu.edu).
M. Nix and M. E. Robinson are with Xilinx Inc., Communication Technology
Division, Austin, TX 78746 USA.
Digital Object Identier 10.1109/JSSC.2004.840955
Fig. 1.
LVDS interface with termination at the receiver and source ends for
gigabits-per-second operation.
technology developed to provide a low-power and low-voltage
alternative [3] to ECL and other high-speed I/O interfaces for
point-to-point transmissions. LVDS achieves higher speed and
signicant power savings by means of a differential scheme for
transmission and termination, in conjunction with low voltage
swing.
In this paper, two low-voltage, low-power, and high-speed
LVDS drivers are discussed. Both drivers can operate with data
rates of 1 Gb/s and above, and they are fully compatible with
IEEE Std 1596.3-1996 [3] for general-purpose links and IEEE
Draft P802.3ae/D5.0 [4] for XSBI interfaces. Section II dis-
cusses the LVDS interfaces, the typical LVDS drivers, and the
design challenges for low-voltage operation. In Section III, the
low-voltage, low-power LVDS drivers are discussed and some
of the simulation results are also presented. The experimental
results and conclusions are addressed in the last two sections.
II. T
YPICAL
LVDS D
RIVERS
An LVDS interface, as shown in Fig. 1, has a low-voltage
swing (250400 mV); it is connected point-to-point and
achieves very high data rates (up to 500 Mb/s per signal pair)
and reduced power dissipation [3]. LVDS uses differential data
transmission and the transmitter is congured as a switched-po-
larity current generator. A differential load resistor at the
receiver end provides optimum line impedance matching.
Due to the imperfect termination, package parasitics, compo-
nent tolerances or crosstalk [5], there are reected waveforms
returning to the driver. As data rates push signicantly above
500 Mb/s and connectors are added, an additional termination
resistor is usually placed at the source end to suppress reected
waves, and the LVDS signaling can be substantially enhanced.
Low voltage differential signaling is a standardized data trans-
mission format that is widely used for serial data transmissions;
as shown in Fig. 2, a differential signal is centered at a common-
mode voltage of about 1.25 V. The maximum magnitude of the
differential signal is 400 mV. Typically, the LVDS signal varies
in magnitude from 1.05 to 1.45 V.
A typical bridged-switches LVDS driver behaves as a cur-
rent source with switched polarity as shown in Fig. 3(a) [3].
The bias current
is switched through the termination resis-
tors according to the data input, and thus produces the correct
0018-9200/$20.00 © 2005 IEEE CHEN et al.: LOW-VOLTAGE LOW-POWER LVDS DRIVERS
473
Fig. 2.
LVDS signal formatting.
Fig.
3.
Typical
LVDS
driver:
(a)
macromodel
and
(b)
transistor
implementation [3].
differential output signal swing. A possible implementation of
the typical LVDS driver is shown in Fig. 3(b). It uses four MOS
switches (M1M4) in a bridged conguration. If switches M1
and M4 are on
, the polarity of the output current
is positive together with the differential output voltage. On the
contrary, if switches M1 and M4 are off (switches M2 and M3
are on), the polarity of the output current and voltage is reversed.
The typical LVDS driver works well if the supply voltage
is 2.5 V or greater. It is simple and only needs minimum
static current consumption to produce the required output signal
swing. But when the supply voltage drops below 2 V (e.g., 1.8 V
for 0.18- m CMOS technology), the typical LVDS driver does
not have enough headroom in the
direction. This is mainly
due to the nite on-resistance of the PMOS transistor switches
and the large amount of current (nominally 6.4 mA for a signal
swing of 320 mV and a 50-
termination resistance) owing
through the switches. The voltage drop across the transistor con-
sumes headroom and it demands relatively high voltage supplies
for the LVDS driver to operate properly.
Fig. 4.
DCS LVDS driver. (a) Model and (b) potential transistor level
realization.
Fig. 5.
SCS LVDS driver model.
III. L
OW
-V
OLTAGE
, L
OW
-P
OWER
LVDS D
RIVERS
A. Double Current Sources (DCS) LVDS Driver
A solution to the headroom issue discussed in Section II is
to remove the top PMOS switches in the typical LVDS driver
[Fig. 3(b)] and replace them by two PMOS current sources,
as shown in Fig. 4(a); We call this structure a double current
sources (DCS) LVDS driver. In order to produce the same signal
swing, the bottom NMOS current source is required to sink
,
which doubles the static current consumption as required by the
output signal swing. Accordingly, the embodiment of Fig. 4(b)
consumes more current than the embodiment of Fig. 3(b). In
addition, the NMOS transistor switches and the bottom NMOS
current source are required to be larger than the corresponding
transistors in Fig. 3(b). If an integrated circuit includes a plu-
rality of LVDS drivers, the increased current consumption and
transistor dimensions may limit their applications. Also, larger
transistor dimensions increase the total pad capacitance and so
reduce the pin bandwidth.
B. Switchable Current Sources (SCS) LVDS Driver
Another solution to the headroom issue is shown in Fig. 5.
Instead of using two constant current sources at the top, two
switchable current sources are used [6]. Depending on the
data input, one of the two switchable current sources will 474
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005
Fig. 6.
SCS LVDS driver with control circuit.
conduct current. This current ows through the termination
resistors and produces the output voltage swing. Notice that the
bottom NMOS current source only needs to sink
, leading to
minimum static current consumption.
Fig. 6 shows the basic principle behind the proposed SCS
LVDS driver. When
, a reference voltage, is applied to the
gate of M1(M2), the transistor conducts a current
, which
is a copy of a well-controll