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Junction Integrity for Low Temperature Dopant Activation in Silicon Watson, Geoff E.
24
th
Annual Microelectronic Engineering Conference, May 2006


7



AbstractDetailed within this paper is investigation of using
low temperature processes to activate dopant in silicon.
Parameters studied include breakdown voltage, turn-on
voltage, leakage current, and ideality factor. Strong
correlation was seen between the temperature of activation and
both the ideality factor and leakage current. Breakdown
voltage seemed constant except for the highest temperature
processing. Turn-on voltage seemed to change for boron
activation, but not for phosphorus activation
Index TermsDoping, electrical activation, semiconductor
process modeling, low temperature processing.
I. I
NTRODUCTION
ntrinsic silicon as a semiconductor lacks the conductivity
to allow for circuits to operate. This is corrected by the
addition of dopants that increase the conductivity. Dopants
are divided into two subgroups: p-type and n-type. The
n-type dopants, such as Phosphorus or Arsenic, when
electrically activated in the silicon provide extra electrons
which allow the silicon to conduct electricity. The p-type
dopants, such as Boron or Gallium, remove electrons when
activated and the resulting hole allows the conduction of
electricity as well.
However, in order for the dopants to become
electrically activated, the silicon must undergo a thermal
process. In the case of thin film transistors where silicon is
found connected to an insulating glass, there are material
constraints that must be considered. For example, Corning
Incorporated produces a glass that has many desirable
characteristics for thin film transistors. The negative
qualities of this glass, however, include its low temperature
strain point of approximately 660°C. While this is
seemingly a high temperature, a comparison with the
activation processing temperatures around 900°C to 1100°C
shows that the glass would be raised far above its strain point
causing irreparable damage to the glass.
Having devised a method of activating the dopant at a
temperature of 600°C, there are still concerns as to how this
affects the electrical devices. This study attempted to
characterize the effects of lowering the temperature for
Manuscript received May 20, 2006. This work was supported in part by
the Rochester Institute of Technology.
G. E. Watson is with the Rochester Institute of Technology, Rochester,
NY 14623 USA (e-mail: gew3076@rit.edu).
dopant activation as it relates to several different
characteristics found in diodes.
II. T
HEORY
A. Low Temperature Activation
In order for the dopant atom to become electrically
activated, it must be substituted in to the silicon lattice in
place of a silicon atom. Normal anneal processes do this by
increasing the temperature of the activation step. The use of
the higher temperatures in the case of the specified Corning
Inc. glass is impossible as it would damage the glass by
raising the temperature over the strain point.
An alternative to raising the temperature of the process
requires a look into why the elevated temperature was
thought necessary. In modern processing, silicon atoms
must be substituted for dopant atoms. This substitution
requires energy. One way to provide this energy is by
elevating the temperature. This temperature increase
provides energy for the silicon to leave the lattice site
wherein the dopant atom is placed. The temperature
increase, therefore, is only required to remove the silicon
atom from the lattice site and place the dopant atom in that
same site.
The alternative processing is to destroy the silicon lattice
before attempting the activation. This amorphization of the
lattice allows the temperature increase to be used to rebuild
the lattice using whatever atoms are nearby. After ion
implanting the dose of dopant atoms, the concentration
allows the energy from the temperature to activate the
dopant atoms while simply rebuilding the lattice. The
temperature required for this is much lower than the standard
processing requiring only 600°C to activate the dopant.
B. Amorphizing the Lattice
As it happens, the implanting of dopant atoms creates an
amount of implant damage which is amorphization of the
silicon. For phosphorus implantation, the atoms being
implanted have enough mass to create a large amount of
amorphization. They are said to self-amorphize the lattice.
However, boron atoms, because of their small mass, when
implanted create very little damage to the lattice. For this
reason, another element must be used to create the damage
desired. For ease, fluorine is used to do this damage. This is
convenient because fluorine is another species of element
located in the source for the boron dopant. Boron trifluoride,
BF
3
, is the gas used by the ion implanter to provide the
boron. Simply turning a dial allows the implantation of the
Junction Integrity for Low Temperature
Dopant Activation in Silicon
Geoff E. Watson
I Watson, Geoff E.
24
th
Annual Microelectronic Engineering Conference, May 2006


8



fluorine as well. The fluorine has more mass which provides
greater implant damage. Lastly, the fluorine does not affect
the electrical properties of the implanted silicon making it an
ideal choice.
III. E
XPERIMENTAL
P
ROCEDURE
A. Diode Creation
To begin this processing, both p-type and n-type wafers
were acquired. The resistivity of the p-type wafers was 15 to
25
-cm and the resistivity of the n-type wafers was 10 to
25 -cm. The wafers began with an RCA clean using the
standard RIT RCA clean process. A pad oxide was then
grown on the wafers in the Bruce furnace. The recipe used
was Furnace Recipe 250 which targeted 500Å. Following
this, well implants were performed on the Varian 350D Ion
Implanter. For the n-type wafers, phosphorus was implanted
at a dose of 5.5x10
12
cm
-2
at an energy of 100 keV. For the
p-type wafers, boron was implanted at a dose of 6.0x10
12
cm
-2
at an energy of 55 keV. A diffusion step was performed
for the well drive and a field oxide was grown using Furnace
Recipe 112. The field oxide target was 5000 Å.
Level 1 lithography was then performed. Two die on each
wafer were shot with the NWELL RIT BJT mask to set
alignment marks. The rest of the die were shot with the
BASE RIT BJT mask. Defaults were used for all of the
exposure parameters. To remove the oxide from the
patterned areas, a 12 minute etch was performed in 10:1
buffered oxide etch. This was followed by a deionized water
rinse for 5 minutes. The resist was stripped using a solvent
strip and an RCA clean was performed to remove any
residual organics. Furnace Recipe 311 was then used to
grow 1000 Å of oxide to be used as an implant mask.
The backside of the wafers were implanted to improve the
contact between the aluminum. N-type wafers were
implanted with phosphorus at a dose of 1x10
15
cm
-2
with an
energy of 92 keV. P-type wafers were implanted with boron
at a dose of 4x10
15
with an energy of 34 keV. Furnace
Recipe 272 was used to anneal the backside implants. The
frontside of the wafers were then implanted to create the
active area. For the n-type wafers, fluorine was first
implanted at a dose of 3x10
15
cm
-2
with an energy of 75 keV
to amorphize the surface. Boron was then implanted at a
dose of 4x10
15
cm
-2
. For the p-type wafers, phosphorus was
implanted at a dose of 4x10
15
with an energy of 92 keV.
The experimental split was performed at the frontside
anneal. The processing conditions can be found in Figure 1.
The recipes used were Furnace Recipes 273 through 279.
Contact cut lithography was then performed using the
CONTACT CUT RIT BJT mask and all the default
parameters for exposure. The contact cut etch was
performed in the same 10:1 buffered oxide etch for 2.25
N-type Wafers
P-type Wafers
600C 1 hr
600oC 1 hr
600oC 2 hr
600oC 2