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HOTLink Jitter Characteristics
fax id: 5109

Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
August 1994 Revised June 13, 1995
HOTLink Jitter Characteristics
Abstract
This application note describes the basics of jitter in transmis-
sion systems and, using HOTLink as the example, shows
how it can be analyzed and measured. Specific characteriza-
tion data is presented that will allow system integrators to
understand the parameters needed to improve the reliability
of their systems.
Introduction
This note examines jitter from three different perspectives.
First, as a background overview, it describes a few basic jit-
ter concepts that affect digital systems. Second, it describes
the jitter performance and characterization of the HOTLink
Transmitter (CY7B923). Third, it describes the jitter tolerance
and feed through characteristics of the HOTLink Receiver
(CY7B933).
Numerical characterization data is supported by descriptions
of the various testing techniques and equipment that are re-
quired to obtain this information. Commercial, custom, and
home-brew test equipment are described along with the
connections used to gather data that illustrates the levels of
performance attainable by HOTLink products.
The data contained in this application note will help users to
understand the various characteristics of link components
and HOTLink characteristics and capabilities. This data is of-
fered to assist in the design of robust serial interconnect links
Jitter
Jitter is a high-frequency semi-random displacement of a sig-
nal from its ideal location. These displacements can occur in
amplitude, phase, and pulse width, and are generally catego-
rized as either deterministic or random. For data communica-
tions links based on (or similar to) HOTLink, measurement
and specification of jitter is usually restricted to timing dis-
placements.
Deterministic jitter are those timing variations that are repeat-
able within a system and whose cause can generally be di-
rectly attributable to specific physical components or events.
An example of this would be the jitter caused by the frequency
selective attenuation and phase delay of a signal in a trans-
mission line.
Random jitter deals with those timing variations that are much
more probabilistic in nature. While still observable and mea-
surable in a system, this jitter is not directly predictable. Com-
mon sources for random jitter are thermal and electrical
noise, both internal to and injected into a system or compo-
nent.
Jitter in logic circuits is often characterized by its transfer
function. This function, known as jitter feedthrough, is a mea-
sure of jitter output relative to jitter input of a system or com-
ponent. Most circuits, when presented with jitter, tend to am-
plify that jitter in a few or many areas. Fortunately for data
communications system (which are plagued by high jitter cre-
ation elements), application of properly designed PLLs
(phase-locked loops) can actually reduce or remove large
amounts of jitter from a clock or data stream.
BackgroundJitter in Logic Systems
The timing of logic signals flowing through a logic system are
often assumed to be a series of simple voltage transitions that
occur after some fixed delay. While this is a convenient and
usually sufficient assumption for the logical function of a de-
vice, it is insufficient to analyze the limits of the timing or the
reliability of the design.
.
Figure 1. Link Jitter Budget Depends on Link Components HOTLink Jitter Characteristics
2
The delay through logic devices (i.e., gates, flip-flops and oth-
er common building blocks) is defined to a first order by the
time it takes for the inputs, the internal circuit nodes, and the
outputs to change from one voltage to another. Since there is
always some uncertainty about the exact voltage present at
any node in the circuit, various logic families have been de-
vised with specific ways to assure reliable logic functions.
Thresholds are well defined and inter-gate links have suffi-
cient voltage margins to assure reliability. Typical compo-
nents have output levels (e.g., Voh, Vol, etc.) that assure a
significant voltage margin above and below the input thresh-
olds (e.g., Vih, Vil, Vth, etc.).
Most logic model libraries document a fairly wide range of
possible delays through a logic element. This range includes
the effects of many internal characteristics such as differenc-
es in output resting voltage, threshold voltage, signal ramp
rates, and (to some extent) the speed the signals travel along
the interconnecting wire, metalization, and leadframes.
These delays, while supposedly covering the minimum to
maximum range for the part, assume specific external oper-
ating and signal conditions. By presenting the logic element
with input, output, or power conditions beyond those assump-
tions, it is possible for these logic elements to exhibit apparent
delays both faster and slower than the specified minimum and
maximum.
The noise carried on the V
CC
or Ground rails (both internal
and external) affect the actual timing of the I/O transition by
causing changes in the starting levels of the active transition.
The illustration in
Figure 2 shows only the timing variation
caused by ground bounce, but the influence of V
CC
noise has
a similar effect. If the signal begins its transition at some ar-
bitrary but fixed time, and has a transition rate (i.e., rise time
or fall time) that is mostly controlled by slew rate limiting ef-
fects not related to the power supply glitch, the effective tim-
ing will be determined by the placement of the glitch. If the
transition begins on a glitch-peak, it will arrive at the threshold
voltage a little early, and if the transition starts in a glitch-val-
ley, it will arrive a little late. This change in timing is usually
invisible to the external examiner (except as power supply
induced timing variation) because much, if not all of the glitch
is contained within the IC package, and is not externally ob-
servable.
The effect of this variation in starting voltage can cause sig-
nificant variations in timing. A signal that has a 1 ns/V ramp
rate (TTL edges are usually between 12 ns/V, and can be
much slower), will have an effective change in delay of about
1 picosecond per millivolt of disturbance. This equates to
±
100 picoseconds of delay variation for
±
100 millivolts of
ground or V
CC
noise, an amplitude which is normally deemed
quiet. When noise spikes approach 1 volt, delay variations
could be expected to exceed 1 nanosecond. With a volt of
power supply variation, other delay effects would surely begin
to appear.
Additional timing variation can be caused by noise coupled
into the external or internal logic through cross coupled logic
paths (including package-pin crosstalk), or by power supply
noise injection. These minor variations in delay are typically
ignored in the analysis of the logical function, since there is
sufficient overdrive (voltage noise margin) to assure that the
logical function is achieved. However this assurance is not
transferred to the timing margins of a logic design.
Most of the delay of todays high performance logic is caused
by an output ramping from its resting voltage to the actual
threshold voltage (the voltage at which the gate begins to
make its logical decision and subsequently change its own
outputs). Any disturbance in either the internal threshold or
the ramping input or output will cause a change in the appar-
ent delay through the gate (see
Figure 3). All single-ended
logic gates suffer from this variable-delay characteristic. Sin-
gle ended circuits include all TTL, CMOS, and any ECL logic
that uses an internal or external threshold reference.
Differential circuitry can be used to partially mitigate the ef-
fects of injected noise, since the threshold of the gate is de-
termined by a complementary output, hopefully carrying the
same injected noise, but ramping in the opposite direction.
The common mode range of such a differential gate helps to
reduce many noise induced delay characteristics. All of the
critical timing paths in HOTLink products are implemented
with differential CML (Current-Mode Logic) signals to mini-
mize crosstalk and V
CC
-coupled noise-jitter effects.
Various design techniques have been developed that maxi-
mize timing margins in logic, but in most of these techniques
the timing of any particular logic element is considered a con-
stant (or a range of constants). Except for the well known
metastability characteristic of storage elements, the design
tools assume that each element has a fixed delay, and the
only accommodation to metastability is to attempt to avoid the
conditions that provoke the unpredictable behavior.
Traditional design practices work on the simple assumption
that if the logic path (delay) between storage elements is less
than the time between clocking edges by some comfortable
margin, then the logic will behave exactly as the designer
intended. As clock speeds increase and as product complex-
ity increases this comfortable simplifying-fantasy becomes
more diffi