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Live at Power-Up: PLD Effects on System Design Live at Power-Up
PLD Effects on System Design
August 2005 Table of Contents
2
Live at Power-Up
System Design Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Circuits and Applications Requiring Short Initialization Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Live at Power-Up Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Programmable Logic Device Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power-Up Device Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
System Functionality Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Level 0 LAPU Contributes to Cost Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Live at Power-Up Devices Active During System Voltage Power Ramp-Up and Before Power-Up . . . 4
Programmable Logic Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power-Up Device Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-Up Behavior of SRAM FPGA and NVM (Antifuse) FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up Behavior of Hybrid SRAM FPGA and NVM (Flash) FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Up to Operation Time NVM vs. SRAM FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-Up to Operation Time - NVM vs. Hybrid SRAM FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Implementation Using Level 2 SRAM FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Implementation Using Level 0 Nonvolatile FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Tables
Programmable Logic Device Power-Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The LAPU Cost Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Live at Power-Up
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System Design Trends
As systems become more complex, pressure to reduce cost and shorter design cycles are the drivers for
higher efficiency, modularity, and simplicity of systems. When a certain feature is required in the
application, designers usually scan the market for possible solutions that could meet system requirements.
Once they narrow down the selection to those solutions that satisfy the design needs, they choose
between the alternatives on the basis of cost and design simplicity.
Circuits and Applications Requiring Short Initialization Time
Once power is applied to a typical system, system components must be initialized and system supervisory
tasks are performed, such as setting up the microprocessor environment, performing critical system
startup tasks, and controlling operation during power ramp-up until system voltages are stable. In a
complex system, system supervisory tasks may include configuring memory blocks; system initialization
tasks might include decoding of the microcontroller address bus, synthesizing and distributing various
clocks to multiple system components, distributing resets or enable signals, managing bus activity
transmissions to avoid data glitches, and performing time critical tasks to minimize processor initialization
time.
Some applications require fast system initialization time to allow immediate operation. Examples include
medical and industrial applications that perform critical operations, such as life assistance equipment.
Battery-operated portable applications with frequent power-up and power-down cycles require short
initialization time to increase product usability for the user. Other critical operation applications that require
instant operation after power-up are automotive engine startup control and military applications such as
missile startup control.
Live at Power-Up Devices
A system is composed of multiple components with inter-dependencies, and the designer's task is to make
sure these components all work together. It is vital to choose live at power-up devices for the systems
critical path in order to achieve efficient system operation. As illustrated in
Figure 1 on page 4
, live at
power-up devices are operational before the system voltage has reached its minimum level, which is
defined as the power-up stage, as opposed to devices that are operational only after power-up. For
example, choosing a live at power-up device that has an integrated phased-locked loop (PLL) for clock
distribution tasks, not only reduces overall system startup time, but also eliminates the need for a
standalone PLL to perform this function.
Selecting live at power-up devices for the critical system startup path minimizes overall application startup
time, cost, size, and reduces design complexity. 4
Live at Power-Up
Programmable Logic Device Alternatives
Programmable Logic Devices (PLDs) have experienced dramatic growth contributed by their benefits of
short time-to-market, in-system programming (ISP) capability, ease of use, and rapid prototyping. The
transition to advanced technologies has resulted in a dramatic cost reduction for PLDs, which are
increasingly replacing live at power-up Application Specific Integrated Circuits (ASICs) in system designs.
When a PLD is required in the system, designers should not ignore the live at power-up attribute of the
chosen PLD. This decision could unnecessarily increase the size and cost of the system.
PLDs require configuration memory to initialize the device for operation. There are differing technologies
for configuring PLD solutions available in the market. PLDs based on nonvolatile memory technologies,
such as Flash, EEPROM, and antifuse, store their configuration on chip. This eliminates the need to
download the configuration, making these devices readily available for operation in a similar way to
Application Specific Standard Products (ASSPs) and ASICs.
Other technologies, such as the volatile SRAM-based programmable logic devices, wake up in an
unknown state and require configuration from an external, nonvolatile memory device on each power-up
cycle. In addition, there are Hybrid SRAM devices that have an SRAM FPGA architecture and a
nonvolatile configuration memory on-chip. These Hybrid FPGAs must be loaded internally on each power-
up cycle. Only after the device is loaded with the configuration, can it start operating according to the
customer application. After each power-down or power supply "brownout," the Hybrid device loses its
configuration and needs to be loaded again in the next power-up cycle.
Figure 2 on page 5
describes the
PLD technology alternatives, which include SRAM, EEPROM, Flash and antifuse, with respect to their
external or internal configuration component.
Live at power-up PLDs simplify the design effort required, and can help initialize and set up the system
environment and prepare for microcontroller and other system operations, hence shortening system
initialization time. Setup activities such as configuring system memories, providing a consistent and
reliable power-up sequence for components on the system board, distributing clocks to devices, and
managing interfaces and bus activity, help make the design more efficient, reduce component count, and
reduce power consumption.
Figure 1: Live at Power-Up Devices Active During System Voltage Power Ramp-Up and Before Power-Up
Time
Power Up
Vol
t
age
System
Voltage
Power On
LAPU
Non-LAPU
Time
Power Up
Vol
t
age
System
Voltage
Power On Live at Power-Up
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Power-Up Device Classification
Actel is using a device classification system that helps designers identify the power-up behavior of
semiconductor devices in a system. This classification system helps designers choose the appropriate
programmable logic components for their applications, taking into account operation and functionality
during power-up stages of the system.
Figure 3 on page 6
shows a typical system power-up operation from the moment a voltage is applied
(power-on), to the point where the voltage reaches the lower operational limit of the system voltage, and
finally the system is initialized. For the purpose of s