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CoE/EE 455 Digital Systems Laboratory Spring 2004 Laboratory #2 Digital Voltmeter Introduction: CoE/EE 455
Digital Systems Laboratory
Spring 2004

Laboratory #2 Digital Voltmeter


Introduction:


Digital multimeters are familiar instruments to modern day engineers. In
particular, in the volts mode they measure potential differences and then display the
result in an easy-to-read decimal format. In this laboratory exercise your mission is to
design and build a primitive, yet useful, digital voltmeter (DVM). Obviously, the core of
a digital voltmeter is an Analog-to-Digital Converter (ADC), which converts the analog
signals that one desires to measure into a digital representation that is then displayed in a
numeric format. High quality analog-to-digital converters are relatively inexpensive and
readily available. In fact, there is a quad 8-bit ADC on your FPGA board right next to the
DACs you used in the previous lab. However, the purpose of this design is to compare
two methods of conversion so we will not use the ADCs (unless you would like to take a
reading with them just to check the accuracy of your algorithm). Never fear!!! This
apparent hurdle is easily overcome. Integrated circuit ADCs are often designed using a
Digital-to-Analog Converter (DAC) and an analog comparator. Control logic is used to
choreograph the analog-to-digital conversions. A block diagram of the system you
must design and build is shown below. For the first design, the 68000, in conjunction
with your carefully designed program, will perform the functions of the control logic.
Once that system is working and carefully tested and documented you will redesign the
control logic in the FPGA so that the 8-bit value that corresponds to the unknown input
level is generated by the FPGA, DAC, and comparator. The 68000 will perform the
conversion from this 8-bit number to a text string indicating the voltage and display the
value in a terminal window on your Sun workstation display for both methods of
generating the 8-bit value (i.e., regardless of whether the 68000 or the FPGA is
determining the 8-bit value).

Comparator
+
-
DAC
Control
Logic
Unknown
Input Level


System Block Diagram


You will program the 68000 (and later, the FPGA) to execute two conversion
algorithms: 1) the linear ramp method and 2) the method of successive
approximation. In both methods, one input of the analog comparator is connected to the
1 unknown input signal and the other comparator input is driven by the output of the DAC,
which in turn is controlled by the control logic (68000 or FPGA). By directing the DAC
to provide the comparator with guesses of the unknown input voltage and observing
the result of the comparison, the input level may be determined. The hardware for the two
methods you will study is identical all that varies is the algorithm for updating the
guesses and zeroing in on the unknown input level.

The Ramp Method of Analog to Digital Conversion


The simpler of the two A/D conversion techniques is the ramp method. In this
method the control logics first guess of the unknown input level is one extreme of the
allowed analog range and each successive guess is one step higher or lower than the last.
After each guess, the output of the comparator is sampled by the control logic. Thus, the
guess of the processor gradually changes, step by step, until it crosses the analog input, at
which point the comparator switches states, the control logic terminates the ramping
process (since the previously unknown input has been determined to within the resolution
of the DAC), and the result is displayed. Although simple, the ramp technique is
relatively slow.

The Successive Approximation Method of Analog to Digital Conversion


The method of successive approximation is a binary search algorithm and
typically decreases the time required to perform the conversion. This algorithm is
frequently used by integrated circuit ADCs.

In this laboratory exercise you will use the Maxim Semiconductor MAX 505
DAC and an LM339 comparator.

Specifications:

Your DVM should make measurements of the voltage present at the ECB X-input BNC
connector. Consequently, you will need to rewire the post labeled X to disconnect it from
the DAC output and connect it to one of the comparator inputs. Here are some additional
specifications:

a)
The DVM should be able to measure input voltages in the range

5 volts < (input voltage) < +5 volts

b)
Display the measured voltage (in volts) in the following format:

xx.yyy Volts

c)
The measurements should be taken and reported at regular time intervals.


DC volts - Displayed value represent the average value computed over the previous time
interval, T. An appropriate value for T would be 100-200 msec. The X¡ are the voltage
2 measurements. N is the number of samples taken in the interval, T. Your N should be at
least 8. A DC level may be computed as follows:
=
=
N
i
i
X
N
DC
1
1


Helpful Hints:

Here are some suggestions that should decrease the time required by your group to
develop your 68000-based DVM.

1. Wire up the DAC and write the routine that updates the DAC. Check for correct
operation of the DAC by repetitively generating a ramp; thereby, generating a sawtooth
waveform. By measuring the period you will be able to determine the maximum
conversion rate possible. Do your best to minimize the period of your ramp. Here is a
chance to really take advantage of the 68000 addressing modes and instruction set!

2. Wire up your comparator and FPGA logic to report the one bit comparison to the
68000. Write a test program to confirm that the comparator output is being read correctly
by the 68000. The comparator is to be powered by +12 and 12 volts. You will need to
design a voltage divider circuit to connect to the open-collector comparator output so that
the FPGA sees +5 or 0 volts when the comparator output is high or low.

3. Write and test your routine to perform analog-to-digital conversion using the ramp
method. Test the routine by applying a DC voltage. Call your routine to make a single
conversion. Examine the result by comparing it to what you read on the digital
multimeter in the lab. Change the DC voltage. Make another conversion. Is the routine
working correctly? Note: the ramp generating code from item 3 above is a good starting
point. All that is needed is a line or two of code that tests the LM339 output and then
takes the appropriate action. Note the worst case conversion time for your system.

4. Write and test a routine to perform analog-to-digital conversion using the method of
successive approximation. Note the conversion time of this method. Be sure that the
DAC output has settled before reading the comparator output! Otherwise you will
get unreliable results.

5. Write and test a routine to convert your 8-bit DAC value to a string of characters to be
output to the terminal on the PC via the serial interface.

NOTE: Do as much designing and programming as possible outside of the lab
period. Try to reserve the lab period for debugging!



Report Content:

3
The content of your report is up to you but here are some issues to ponder.
Providing answers to these questions will go a long way toward writing an effective
report.

1. What is the highest conversion rate possible using the ramp method? How about for
the method of successive approximation? How many instruction cycles (worst case)
do each of the methods require to perform a single conversion? Which method is better
and why? Include a clear and complete analysis of why you observe the performance
ratio from above rather than some theoretical ratio. Achieving a particular ratio is NOT a
goal! What is important is to analyze and explain why a different ratio is observed. Note
the difference in conversion rate ratios for the two algorithms between the 68000
implementation and the FPGA implementation. Are these different? If so, why? Be sure
to document the execution times of both methods with appropriate oscilloscope traces
that clearly show the desired timing.

2. What was the limiting factor for each method? Is the conversion rate determined by
the hardware (i.e., the DAC and the comparator settling times) or the 68000 clock rate
and software? You should support your conclusion with hard evidence, such as scope
traces etc. To answer this think of gradually increasing the 68K clock (or the FPGA
clock) frequency until errors occur. Which of the three blocks in Fig. 1 above cause the
system to fail first? Can you propose any hardware/software modifica