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ISL6113, ISL6114 1
®
Dual Slot PCI-E Hot Plug Controllers
The ISL6113, ISL6114 both target the PCI-Express Add-in card
hot swap application. Together with a pair of N-Channel and
P-Channel MOSFETs, and two sense resistors per slot, either
provides compliant hot plug power control to any combination
of two PCI-Express X1, X4, X8 or X16 slots.
The ISL6113, ISL6114 feature a programmable current
regulated (CR) maximum level for a programmable period to
each voltage load so that both fault isolation protection and
imperviousness to electrical transients are provided.
For each +12V supply, the CR level is set by a resistor value
depending on the needs of the PCI-Express connector (X1, X4,
X8 or X16) to be powered. This resistor is a sub-ohm standard
value current sense resistor one for each slot and the voltage
across this resistor is compared to a 50mV reference providing
a nominal CR protection level adequately above the specific
slot maximum limits. The 3.3V supply uses a 15m sense
resistor compared to a 50mV reference to provide 3.3A of
maximum regulated current to all connector sizes. The
3.3VAUX is internally monitored and controlled to provide a
nominal maximum of 1A of AUX output current.
The CR period for each slot is set by a separate external
capacitor on the associated CFILTER pin. Once the CR period
has expired, the IC then quickly turns off its associated FETs
thus unloading the faulted card from the supply voltage rails. A
nominal 3.3V must always be present on the AUXI pin for
proper IC bias; this should be the 3.3VAUX supply if used, if not
the AUXI pin is tied directly to the 3VMAIN supply. Both ICs
employ a card presence detection input that disables the MAIN
and AUX enabling inputs if it is not pulled low. Output voltage
monitoring with both PCI-E Reset Not and Power Good Not
reporting along with OC Fault reporting are provided. Whereas
the ISL6113 has the same GATE drive and response
characteristics as the ISL6112, the ISL6114 has a lower turn-on
GATE drive current allowing for the use of smaller
compensation capacitors and thus much faster response to
Way Overcurrent (WOC) conditions. Additionally, the ISL6114
does not turn-on with the CR feature invoked as do the
ISL6112, ISL6113 allowing for shorter CR programmed
periods.The ISL6113, ISL6114 are footprint compatible for all
common pins, but not entirely function compatible with the
ISL6112s QFN package as there are I/O differences.
Features
Dual PCI-E Slot Hot Swap Power Control and Distribution
Highest Accuracy External R
SENSE
Current Monitoring
On Main Supplies
Programmable Current Regulation Protection Function for
X1, X4, X8, X16 Connectors
Programmable Current Regulation Duration
Programmable In-rush Protection During Turn-On
Latch-off or Retry Modes After Failure
Pb-free (RoHS Compliant)
Applications
PCI-Express Servers
Power Supply Distribution and Control
Hot Swap/Electronic Breaker Circuits
Network Hubs, Routers, Switches
Hot Swap Bays, Cards and Modules
FIGURE 1. TYPICAL ISL6113, ISL6114 BLOCK DIAGRAM
APPLICATION IMPLEMENTATION
3VGATEA
3VINA
12VGATEA
12VINA
ISL6113, ISL6114
3VSENSEA
VSTBYB
VAUXA
12VSENSEA
3VGATEB
3VINB
12VGATEB
12VINB
3SENSEB
VAUXB
12VSENSEB
PRSNTA
PRSNTB
FORONA
FORONB
AUXENB
ONB
ONA
GPI_A0
GPI_BO
GPO_A0
GPO_B0
FAULTA
FAULTB
PWRGDA
PWRGDB
CFILTERA
PERSTB
PERSTA
GND
12VOUTA
3VOUTA
3VOUTB
12VOUTB
CFILTERB
VSTBYA
IF 3.3VAUX NOT
IMPLEMENTED
AUXENA
IF 3.3VAUX NOT
IMPLEMENTED

FN6457.0
ISL6113, ISL6114
Data Sheet
September 25, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN6457.0 2
FN6457.0
September 25, 2007
Pinout
ISL6113, ISL6114
(48 LD QFN)
TOP VIEW
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL6113IRZA
ISL6113 IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6113IRZA-T*
ISL6113 IRZ
-40 to +85
48 Ld 7x7 QFN Tape and Reel
L48.7x7
ISL6114IRZA
ISL6114 IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6114IRZA-T*
ISL6114 IRZ
-40 to +85
48 Ld 7x7 QFN Tape and Reel
L48.7x7
ISL6113EVAL1Z
ISL6113 Evaluation Platform
ISL6114EVAL1Z
ISL6114 Evaluation Platform
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
GND
(Exposed bottom pad)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
GND
(EXPOSED BOTTOM PAD)
GN
D
3VO
U
T
A
V
AUXA
3V
G
A
T
E
A
3VS
E
NSEA
GPO
_
A0
GPO
_
B0
3VO
U
T
B
V
AUXB
3V
G
A
T
E
B
3VS
E
NSEB
AU
X
E
NA
GND
ONA
ONB
AU
X
E
NB
PE
RST
B
PRSNT
A
PRSNT
B
GPI
_
B0
FAULTB
CFILTERB
12VGATEB
GND
12VINB
PWRGDB
12VSENSEB
FORCE_ONB
12VOUTB
VSTBYB
3VINB
FAULTA
CFILTERA
12VGATEA
GPI_A0
12VINA
PWRGDA
NC
12VSENSEA
FORCE_ONA
12VOUTA
VSTBYA
3VINA
L/
R
PERS
T
A
NC
NC
NC
ISL6113, ISL6114 3
FN6457.0
September 25, 2007
Functional Block Diagram (1 Channel)
LOGIC
VAUX
PWRGD
THERMAL
SHUTDOWN
ON/OFF
VAUX CHARGE
PUMP AND
MOSFET
VAUX
OVERCURRENT
3VIN
10.5V
2.8V
12VIN
12V BIAS
POWER-ON
RESET
250µs
3V
UVLO
12V
UVLO
ON
/OF
F
ON/OFF
ON/OFF
ON/
50mV
50mV
100mV*
100mV*
VSTBY
IREF
VSTBY
40k
x 2
12VGATE
VAUX
3VGATE
FAULT
PWRGD
3VOUT
12VOUT
3VPWRGD
12VPWRGD
INT
GND
PRSNT
L/R
GPO
GPI
FORCE_ON
CFILTER
3VIN
3VSENSE
12VIN
12VSENSE
ON
AUXEN
VSTBY
VSTBY
UVLO
OFF
1.25V
BOTH A AND B SLOTS SHARE THE L/R PIN.
PERST
ISL6113, ISL6114 4
FN6457.0
September 25, 2007
Pin Descriptions
PIN
NAME
FUNCTION
9, 28
FORCE_ONA,
FORCE_ONB
Asserting a FORCE_ON input low will turn on the MAIN and AUX supplies to the respective slot in a forced mode
over riding the ON input and the UV, OC and short circuit protections on those outputs. UVLO protection for the
VSTBY input is not affected by the FORCE_ON pins. Asserting FORCE_ON will cause the PWRGD and FAULT
outputs to enter their open-drain state. This input is internally pulled high to the VAUX rail. Functionality is disabled
when PRSNT is high.
44, 43
ONA, ONB
Enable input for MAIN outputs use to enable or disable MAIN voltage supply (12V and 3.3V) outputs. Taking ONX
low after a fault resets the respective slots Main Output Fault Latch. Functionality is disabled when PRSNT is high.
45, 42
AUXENA, AUXENB 3.3VAUX Enable Input, enables the respective VAUX output. Pulling AUXENX low after a fault resets the
associated slots VAUX fault latch. Functionality is disabled when PRSNT is high.
5, 32
12VINA,12VINB
Connect to 12VMAIN supply and high side of sense resistor. This is one of two pins for Kelvin connection to
measure the 50mV CR Vth. An undervoltage lockout prevents the IC main supply function until 12VIN >10V. The
current regulation threshold is set by connecting a sense resistor between this pin and 12VSENSE. When the
current-limit threshold of IR = 50mV is reached, the 12VGATE pin is modulated to maintain a constant 50mV
voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is
maintained for CR duration, the circuit breaker is tripped and both GATE pins for the affected slot turn off the
switch FETs and thus turn off the supplies to the slot.
8, 29
12VSENSEA,
12VSENSEB
12V current sense low side input. This is the second of two pins for Kelvin connection to the R
SENSE
to measure
the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and
associated 12VIN pin.
10, 27
12VOUTA,
12VOUTB
12V output voltage monitor for UV condition. This is the voltage input downstream of the MOSFET that is delivered
to the add-in card load.
12, 25
3VINA, 3VINB
Connect to 3VMAIN supply and high side of sense resistor. This provides one of two pins for Kelvin connection to
measure the 50mV CR Vth. Undervoltage lockout (UVLO) prevents turn-on until 3VIN >2.75V. The current
regulation threshold is set by connecting a sense resistor between this pin and 3VSENSE. When the current-limit
threshold of IR = 50mV is reached, the 3VGATE pin is modulated to maintain a constant 50mV voltage across the
sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for the
CR duration, the circuit breaker is tripped and both FETs for the affected slot are turned-off.
13, 24
3VSENSEA,
3VSENSEB
3.3V current sense low side input. This provides the second of two pins for Kelvin connection for measuring the
50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated
3VINX pin.
16, 21
3VOUTA,
3VOUTB
3.3V output voltage monitor for UV condition. This is the voltage downstream of the MOSFET that is delivered to
the add-in card load.
1, 36
FAUL