sonic
Applications
R. Chebli and M. Sawan
PolySTIM Neurotechnology Laboratory,

Department of Electrical Engineering, École Polytechnique de Montréal

robert.chebli@polymtl.ca

ABSTRACT- This paper concerns the design and implementation
of a fully integrated High Voltage CMOS DC-DC Up Converter
(VHVUC) dedicated to ultrasonic transmitters. This VHVUC new
topology, followed by a drive amplifier, is based on a multiple-
stage charge pump circuit and a level-up Shifter is used in each
stage as a clock generator in order to increase exponentially the
DC voltage. A drive amplifier, based on a level-up stage and a
class D switching output stage. It is used to excite the ultrasonic
transducer, resonate at 3.5 MHz. Simulation results of the
proposed converter, using a 0.8µm CMOS/DMOS High-Voltage
process technology, show output voltage of 200 V with 83% gain
voltage factor and a 95 mV output ripples for 2 MHz frequency.
Also, the drive amplifier for single shock excitation show a 140 V
spike at the transducer element with a pulse repetition time of
260µs and a rise and fall times of 220 ns and 713 ns respectively
with a peak current through the transducer element of 25 mA.
These results show the feasibility of applying HV process
technology to replace conventional electronic transmitter
technology.

I. INTRODUCTION
Medical ultrasound is used routinely in most hospitals for
diagnosing soft tissue structures. The advantages of the technique
are its lowest cost, real-time image formation, mobility,
noninvasive nature, and no known bioeffects in the used frequency
range [1]. The miniaturization of such ultrasonic systems provide
low power dissipation, good bulk, and low weight [2].
In diagnostic ultrasonic applications, DC level higher or equal to
200 Volts must be applied to reach a large depth in human body
[3]. To generate the required high DC voltage, several circuits
were designed. Some of those are based on coupled-inductor to
achieve the high voltage gain [4], others based on capacitor chains,
which are interconnected by diodes and coupled in parallel with
two non-overlapping clocks [5]. Also, electromagnetic
transformers were designed to generate the required high voltage
[6]. However, all of the previous designs are made on PCBs using
discrete components.
We propose in this paper a fully integrated HVCMOS DC-DC
converter followed by a drive amplifier dedicated to drive MEMS
based ultrasound cells. This system on chip (SoC) device is
intended to build a hand-held ultrasonic system.

Section II presents the design of the fully integrated VHVUC.
Drive amplifier is reported in section III. The simulation results are
shown in section IV, and conclusions are the subject of section V.

II. DESIGN OF THE VHVUC
The block diagram of the VHVUC, based on a 5-stage voltage
doubler, is shown in figure 1. A level-up Shifter is used in each
stage as a clock generator in order to increase exponentially the
voltage. By cascading n voltage-doublers, the output voltage of
the btained VHVUC can be expressed as follows :


(
)
clk
in
n
out
V
V
V
+
= 1
2

(1)

where V
in
and V
clk
are the amplitude of the input and the clock
signals respectively and n is the number of stages.
Each stage consists of a voltage doubler circuit, a voltage level
up Shifter and a level up stage. The voltage doubler circuit shown
in figure 2 is composed of a cross-connected HVNMOS
transistors M
1
-M
2
and the pair HVPMOS transistors M
3
-M
4
used,
as serial diode, to transfer the charge from one stage to the next.
Two phase non-overlapping clocks CK
1
, CK
2
are used to drive
the pumping capacitors (C
1
, C
2
) of each stage. In the voltage
doubler circuit, the use of the N-type transistors improves the
performance of the charge pumping due to its faster carriers
(electrons versus holes), smaller size and less parasitic capacitors.
Its threshold voltage (V
T
) causes a problem for low voltage
application, but for high voltage, this problem is avoided.
By using a faster configuration of cross-coupled HVNMOS
transistors with fast operating clock frequency and less parasitic
capacitors improves the gain voltage of each stage. This
configuration leads to an automatic reverse biasing of the
parasitic bipolar transistors (lateral, vertical) [7].

Stage 2
Stage 3
Stage 4
Stage 5
Stage 1
Vin
Vout
CK1
CK2
Cout
Iout


Fig. 1 Simplified block diagram of the proposed DC-DC up converter

A. Technology process

Today the Double Diffused Metal Oxide Semiconductor (DMOS)
transistor has become the primary choise for high-voltage
integrated circuits. By employing RESURF techniques, it is
possible to combine low-voltage (LV) standard CMOS logic with
high-voltage (HV) output stages where the voltage switching
capability exceeding 400V [8]. The adopted process for the
present work is the 0.8µm 5V/HV CMOS/DMOS process (with
three metal layers) triple wells provided by DALSA
Semiconductor. This smart process consists of modifiying a low-
voltage CMOS technology to accommodate a high-voltage
option. High-voltage capability is obtained when combining the
existing technological layers in an unconventional way in order to
create low concentration doping regions. Cross-section of n- and p-channel HV-devices are given in figure 3. The HV NDMOS
transistor has the source and channel regions, including the thin
gate oxide, identical to those of standard NMOSs. Its V
T
and
transconductance are controlled by the same parameters as the
NMOSs.

D
D
D
S
S
S
M1
S
M2
Vlow
Vhigh
M4
M3
C1
C2
Low to high voltage level up
shifter
Level up stage
D
Vlow
CK1
CK2
V1
V2
CK1b
CK2b


Fig. 2 Schematic of one stage voltage doubler circuit

However, in order to withstand high drain-to-source voltage (V
DS
),
the drain is separated from the edge of the channel P-base by a
lightly doped P-drift and buffer region formed by the HVN-Well
implant. It is important to note that, since the gate oxide is the
same as that of standard LV devices, the maximum V
GS
cannot
exceed 10V. For the HV PMOS transistor, the drain is separated
from the edge of the channel HVN-Well by a low doping
concentration P-drift region in order to withstand high V
DS
. The
DALSA process has two types of HVNMOS devices. The high
side floating source which is connected to its local bulk and can
withstand 100V and its Breakdown (BV
DS
) is
120V. The other
type is the low side one and its source is also connected to its local
bulk which is connected to P-sub and can withstand few volts and
its BV

is
300V. The source-drain BV for HVPMOS is 400V. It
is important to note that when the bulk-source voltage (V
BS
) is 0V
for HV transistors, they have a unidirectional functionality.


G
D
S
B
H
V

HVN-Wel</b>l
P-drift
P-sub
n+
n+
P+
P-base
drain
source
gate



(a)

G
D
S
B
H
V

HVN-Wel</b>l
P-drift
P-sub
p+
p+
n+
drain
source
gate

(b)
Fig. 3 Cross-sections of HV devices and corresponding symbols: (a) HV
NMOS, (b) HV PMOS
B. Operation of voltage doubler circuit
To create a boosting DC voltage using the standard technologies,
the n and p type transistors in the conventional voltage doubler
circuit, are used like a switch where its breakdown voltages drain-
source and bulk are limited by the technologies. To create a
boosting high DC voltage, the conventional exponentially voltage
doubler circuit [9] should be modified to meet the DALSA
technology criteria of high voltage operation. Given that a HV
transistor is unidirectional and cannot be used like a switch, a
solution is adopted which is based on the use of the internal
junction of the HV transistor. In fact, when a high voltage is
applied on the floating source of the HVNMOS (figure 3a) with a
low voltage on its drain, the diode formed by the P-base/HVN-
Well junction conducts and transfers the HV signal to the drain.
Similar for a HVPMOS transistor (figure 3b), when a HV is
applied on its drain and a low voltage on its source, the diode
formed by P-drift/HVN-Well junction conducts and tranfers the
HV to its source. By using the HV transistors as switches in the
voltage doubler circuit, the pumping capacitors cannot maintain a
voltage higher than the input stage voltage due to the previous
explanation. Doing so, the HV N and P type transistors are
connected like it is shown in figure 2 and act as diodes with its
dynamic resistor (R
D
), and inherent constant diode voltage V are
controlled by gate-source voltage (V
GS
). By increasing V
GS
, the
carrier profil will change and the R
D
and V will decrease.
The adapted votage doubler includes a level up shifter used in
each stage of the VHVUC as a clock booster in order to increase
the voltage exponentially by every stage which becomes power
supplies for following cascaded stages. Its output are two phase
non-overlapping clocks (CK
1
and CK
2
) of which amplitudes are
enlarged to (0, V
low
). During the first half cycle, CK
1
= V
low
, CK
2

= 0, the internal diodes of M
1
and M
4
condut; C
2
is charged to
V
low
through the M
1
diode, while C
1
is discharged to V
high
(2
V
low
), through M
4
. During the second half cycle, CK
1
= 0, CK
2
=
V
low
, the internal diodes of M
2
and M
3
condut; C
1
is charged to
V
low
through the M
2
diode, while C
2
is discharged to V
high
(2
V
low
), through M
3
. A voltage gain is therefore obtained between
V
l