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HIP4020 1
®
FN3976.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1997, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4020
Half Amp Full Bridge Power Driver for
Small 3V, 5V and 12V DC Motors
In the Functional Block Diagram of the HIP4020, the four
switches and a load are arranged in an H-Configuration so
that the drive voltage from terminals OUTA and OUTB can
be cross-switched to change the direction of current flow in
the load. This is commonly known as 4-quadrant load
control. As shown in the Block Diagram, switches Q1 and Q4
are conducting or in an ON state when current flows from
V
DD
through Q1 to the load, and then through Q4 to terminal
V
SSB
; where load terminal OUTA is at a positive potential
with respect to OUTB. Switches Q1 and Q4 are operated
synchronously by the control logic. The control logic
switches Q3 and Q2 to an open or OFF state when Q1 and
Q4 are switched ON. To reverse the current flow in the load,
the switch states are reversed where Q1 and Q4 are OFF
while Q2 and Q3 are ON. Consequently, current then flows
from V
DD
through Q3, through the load, and through Q2 to
terminal V
SSA
, and load terminal OUTB is then at a positive
potential with respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A
and B Input Controls. The ILF output is an Overcurrent Limit
Fault Flag Output and indicates a fault condition for either
Output A or B or both. The V
DD
and V
SS
are the Power
Supply reference terminals for the A and B Control Logic
Inputs and ILF Output. While the V
DD
positive power supply
terminal is internally connected to each bridge driver, the
V
SSA
and V
SSB
Power Supply terminals are separate and
independent from V
SS
and may be more negative than the
V
SS
ground reference terminal. The use of level shifters in
the gate drive circuitry to the NMOS (low-side) output stages
allows controlled level shifting of the output drive relative to
ground.
Features
Two Independent Controlled Complementary MOS Power
Output Half H-Drivers (Full-Bridge) for Nominal 3V to 12V
Power Supply Operation
Split
±Voltage Power Supply Option for Output Drivers
Load Switching Capabilities to 0.5A
Single Supply Range +2.5V to +15V
Low Standby Current
CMOS/TTL Compatible Input Logic
Over-Temperature Shutdown Protection
Overcurrent Limit Protection
Overcurrent Fault Flag Output
Direction, Braking and PWM Control
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
DC Motor Driver
Relay and Solenoid Drivers
Stepper Motor Controller
Air Core Gauge Instrument Driver
Speedometer Displays
Tachometer Displays
Remote Power Switch
Battery Operated Switch Circuits
Logic and Microcontroller Operated Switch
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
HIP4020IB
HIP4020IB
-40 to 85
20 Ld SOIC
M20.3
HIP4020IBZ
(Note)
HIP4020IBZ
-40 to 85
20 Ld SOIC
(Pb-free)
M20.3
HIP4020IBZT
(Note)
HIP4020IBZ
-40 to 85
20 Ld SOIC
Tape and Reel
(Pb-free)
M20.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Data Sheet
December 20, 2005 2
FN3976.3
December 20, 2005
Pinout
HIP4020 (SOIC)
TOP VIEW
Block Diagram
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
NC
ILF
B2
ENB
B1
V
SS
A1
ENA
A2
NC
NC
NC
OUTB
V
SSB
V
DD
V
SSA
OUTA
NC
V
DD
NC
V
SSB
V
DD
OUTB
LO
A
D
OUTA
B1
B2
ENB
A1
A2
ENA
ILF
V
SS
V
SSA
Q1
Q3
Q2
Q4
CONTROL
LOGI
C B
CONTROL
LOG
I
C A
I
SENSE
T
SENSE
I
SENSE
I
SENSE
I
SENSE
OV
ER TE
MP
. AND CURRE
NT L
I
MIT
,

LEV
E
L
SHIFT
,
DRIV
E CO
NTROL
HIP4020 3
FN3976.3
December 20, 2005
Absolute Maximum Ratings
Thermal Information
Supply Voltage; V
DD
to V
SS
or V
SSA
or V
SSB
. . . . . . . . . . . . .+15V
Neg. Output Supply Voltage, (V
SSA
, V
SSB
) . . . . . . . . . . . . (Note 1)
DC Logic Input Voltage (Each Input) . . . (V
SS
-0.5V) to (V
DD
+0.5V)
DC Logic Input Current (Each Input)
. . . . . . . . . . . . . . . . . . . . .±15mA
ILF Fault Output Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15mA
Output Load Current, (Self Limiting, See Elec. Spec.)
. . . . ±I
O(LIMIT)
Operating Conditions
T
A
= 25°C
Typical Operating Supply Voltage Range, V
DD
. . . . . . . +3 to +12V
Low Voltage Logic Retention, Min. V
DD
. . . . . . . . . . . . . . . . . . . .+2V
Idle Supply Current; No Load, V
DD
= +5V. . . . . . . . . . . . . . . .0.8mA
Typical P+N Channel r
DS(ON)
, V
DD
= +5V, 0.5A Load . . . . . . . . 2 Thermal Resistance (Typical, Note 2) JA
(°C/W)
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . .
105
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(Lead Tips Only)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. V
SS
is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference
to the V
SS
common ground by using a split supply for V
DD
(positive) to V
SSA
and V
SSB
(negative). For an uneven split in the supply voltage,
the Maximum Negative Output Supply Voltage for V
SSA
and V
SSB
is limited by the Maximum V
DD
to V
SSA
or V
SSB
ratings. Since the V
DD
pins
are internally tied together, the voltage on each V
DD
pins must be equal and common.
2. JA
is measured with the component mounted on an evaluation PC board in free air.
3. Refer to the Truth Table and the V
EN
to V
OUT
Switching Waveforms. Current, I
O
refers to I
OUTA
or I
OUTB
as the Output Load current. Note that
ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1, B2, ENB
inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows a typical
application circuit used to control a DC Motor.
Electrical Specifications
T
A
= 25°C, V
DD
= +5V, V
SSA
= V
SSB
= V
SS
= 0V, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage Current
I
LEAK
V
DD
= +15V
-
-
25
nA
Low Level Input Voltage
V
IL
V
SS
-
0.8
V
High Level Input Voltage
V
IH
2
-
V
DD
V
ILF Output Low, Sink Current
I
OH
V
OUT
= 0.4V, V
DD
= +12V
15
-
-
mA
ILF Output High, Source Current
I
OL
V
OUT
= 11.6V, V
DD
= +12V
-
-
-15
mA
Input Capacitance
C
IN
-
2
-
pF
P-Channel r
DS(ON)
, Low Supply Voltage
r
DS(ON)
V
DD
= +3V, I
SOURCE
= 250mA
-
1.6
2.1 N-Channel r
DS(ON)
, Low Supply Voltage
r
DS(ON)
V
DD
= +3V, I
SINK
= 250mA
-
1
1.5 P-Channel r
DS(ON)
, High Supply Voltage
r
DS(ON)
V
DD
= +12V, I
SOURCE
= 400mA
-
0.6
1.2 N-Channel r
DS(ON)
, High Supply Voltage
r
DS(ON)
V
DD
= +12V, I
SINK
= 400mA
-
0.5
1.1 OUTA, OUTB Source Current Limiting
I
O(LIMIT)
V
DD
= +6V, V
SS
= 0V, V
SSA
= V
SS
B
= -6V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-I
O(LIMIT)
V
DD
= +6V, V
SS
= 0V, V
SSA
= V
SS
B
= -6V
480
800
1500
mA
Idle Supply Current; No Load
I
DD
-
0.8
1.5
mA
OUTA, OUTB Voltage High
V
OH
I
SOURCE
= 450mA
4.2
4.5
-
V
OUTA, OUTB Voltage Low
V
OL
I
SINK
= 450mA
-
0.4
0.6
V
OUTA, OUTB Voltage High
V
OH
V
DD
= +3V, I
SOURCE
= 250mA
2.415
2.6
-
V
OUTA, OUTB Voltage Low
V
OL
V
DD
= +3V, I
SINK
= 250mA
-
0.25
0.375
V
OUTA, OUTB Source Current Limiting
I
O(LIMIT)
V
DD
= +12V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-I
O(LIMIT)
V
DD
= +12V
480
800
1500
mA
OUTA, OUTB Source Current Limiting
I
O(LIMIT)
V
DD
= +3V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-I
O(LIMIT)
V
DD
= +3V
480
800
1500
mA
HIP4020 4
FN3976.3
December 20, 2005
Thermal Shutdown
T
SD
-
145
-
°C
Response Time: V
EN
to V
OUT
Turn-On: Prop Delay
t
PLH
I
O
= 0.5A (Note 3)
-
2.5
-
µs
Rise Time
t
r
-
4
-
µs
Turn-Off: Prop Delay
t
PHL
-
0.1
-
µs
Fall Time
t
f
-
0.1
-
µs
Electrical Specifications
T
A
= 25°C, V
DD
= +5V, V
SSA
= V
SSB
= V
SS
= 0V, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
12, 19
V
DD
Positive Power Supply pins; internally common and externally connect to the same Positive Supply (V+).
15
V
SSA
Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the Supply
(V-).
16
V
SSB
Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the Supply
(V-).
6
V
SS
Common Ground pin for the Input Logic Control circuits. May be used as a common ground with V
SSA
and
V
SSB.
8, 5
A1, B