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Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

Scaling Analysis of On-Chip Power Grid Voltage
Variations in Nanometer Scale ULSI


AMIR H. AJAMI,
1*
!
KAUSTAV BANERJEE
2
AND MASSOUD PEDRAM
3


1
Magma Design Automation, 5460 Bay Front Plaza, Santa Clara, CA 95054
2
ECE Dept., 4151 Eng I, Univ. of California at Santa Barbara, Santa Barbara, CA 93106
3
EE-Systems Dept., 3740 McClintock Ave, Univ. of Southern California, Los Angeles, CA 90089
Email:
1
amira@magma-da.com,
2
kaustav@ece.ucsb.edu,
3
pedram@ceng.usc.edu




Abstract
*
- This paper presents a detailed scaling analysis of the power supply distribution network
voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect
technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering
and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage
drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling,
and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion
which are typically used in the present design methodologies may be insufficient to limit the voltage
fluctuations over the power grid for future technologies. It is also shown that such voltage drops on
power supply lines of switching devices in a clock distribution network can introduce significant amount
of skew which in turn degrades the signal integrity.


Key words
: technology scaling, power distribution network, voltage drop, de-coupling capacitance,
thermal gradient, surface scattering, barrier thickness, clock skew


*
Corresponding Author
!
This work was done when the author was with the Dept. of EE-Systems, University of Southern California.
1

Introduction
Recent advances in CMOS process technology towards 90nm regime and below have highlighted the
importance of signal integrity as one of the main challenges facing todays chip designers. With
increasing operating frequencies and elevating power consumptions in VLSI circuits, the design and
analysis of on-chip power distribution networks has become a critical design task [1],[2]. Aggressive
interconnect scaling has increased the average current density and the resistance per unit length of wires.
Since the supply voltage level is also reduced with the technology scaling, the power supply noise
becomes even more pronounced because the ratio of the peak noise voltage to the ideal supply voltage
level increases with each scaled technology node. The power supply noise mainly manifests itself as a
voltage drop in the power distribution networks and can adversely influence the performance of the signal
nets, especially the clock distribution networks [2],[3]. Any kind of voltage drop in the on-chip power
distribution network should be bounded to the pre-defined device noise-margin limits. An excessive
voltage drop in the power grid may result in a functional failure in dynamic logic and a timing violation in
static logic. For example, it has been shown that a 10% voltage drop in a design with technology feature
size of 0.18
mm, increases the propagation delay of the switching devices by up to 8% [1],[4]. As a result,
the main challenge in the design of the power distribution network is to achieve a minimum acceptable
voltage fluctuation across the chip (about 10% of the nominal supply voltage) while satisfying the
electromigration (EM) reliability rules for the power network segments and to realize such a power
distribution network with minimum routing area of the interconnect metal layers [5],[6],[7].


The effective voltage drop on a chip is attributable to two factors: a) the resistive voltage drop (on-
chip IR drop) which is mostly due to the voltage drop due to on-chip interconnect line resistances and b) the inductive voltage drop (or the di/dt noise) which is mostly caused by the pin-package inductances.
The di/dt, also referred to as simultaneous switching noise (SSN) or ground bounce, is caused by rapid
changes in the current passing through the parasitic inductors in the power network. It should be noted
that solving for IR and di/dt drop separately and adding them to determine the worst-case voltage drop
tends to be overly pessimistic because the worst-case corner for these two contributing factors seldom
occurs. Hence, integrated package and chip level power supply network models are needed to accurately
analyze the voltage fluctuations caused by each factor [8]. The main issue in the analysis of power
distribution network is the huge size of the problem. Simulating all the nonlinear devices in the chip
together with the entire power grid is computationally infeasible. Thus, simulation is usually carried out
in two separate steps. First, all devices are simulated with an accurate non-linear simulator assuming a
perfect supply voltage for each device. As a result, the current drawn by each device connected to the
supply voltage is calculated. Next, devices are modeled as independent time-varying current sources. The
problem of power grid analysis is thereby reduced to that of solving a linear resistive network [6],[7]. The
error incurred by ignoring the non-linearity of devices is usually negligible after a few iterations [3],[7].
Notice that because the actual voltage supplied to each device is lower than the perfect voltage assumed
during the non-linear simulation step, this methodology overestimates the currents drawn by each device,
and therefore, tends to overrate the voltage drop. Model of the power grid in this methodology is fairly
simple; it comprises of a linear network of resistances that models the power grid interconnect segments
and, constant current sources that model the peak current of devices that are connected to the power grid
nodes. Numerous methods have been proposed to either determine the peak voltage drop in the power
supply network efficiently [3],[5],[7],[9],[10], or to reduce the peak voltage drop in the power distribution
network [5],[6],[11].

Wire-sizing is probably the most common method to reduce the overall peak voltage drop by
reducing the resistivity of interconnect lines. Although with up-sizing of the widths of power network
lines, one should be able to reduce the peak voltage drop, the amount of wire segment up-sizing in the
power network is limited by the routing areas that are allocated to the power network in each routing layer
(assuming that the EM rules are satisfied) [6]. In addition to the wire-sizing technique, in order to reduce
the effect of switching noise on the power distribution network, decoupling capacitors are often added
near the switching devices. These capacitors act as local charge reservoirs for switching circuits and
reduce the effect of the power supply glitches and ground bounce. Determining the optimal values and
locations of the on-chip decoupling capacitors is essential in maintaining a robust power supply network
[11],[12]. Similar to the wire-sizing, the portion of the substrate area assigned to the decoupling
capacitances is limited and designers should always consider the tradeoff between the reduction of the
switching noise and the increase in chip area due to insertion of the decoupling capacitors.


It is well-known that through technology-scaling and as a result of reduction of the minimum
interconnect widths, the resistance per unit length of the metal layers increases rapidly. However,
additional physical effects such as electron surface scattering and finite barrier thickness contribute
significantly to the overall metal resistivity of the local thin lines. In fact these effects become even more
pronounced by scaling down of the technology feature size (especially in the Cu interconnects).
Furthermore, it has been shown that as the technology feature size is reduced, the peak chip temperatures
that occur on the global metal layers increase rapidly due to the self-heating effect [13]. This will cause a
further increase in the metal resistivity. Any increase in the metal resistivity would be translated to an
increase in the voltage drop in the power distribution network through the IR-drop effect.

Most of the recent research reports on the voltage drop effect have focused on the methodology for
efficient computation