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Newsroom - Welcome to Novas Notes a monthly e-mail newsletter distributed to our customers partners and friends We hope the information in this newsletter will help you use our products more effectively in
Newsroom - Welcome to Novas Notes a monthly e-mail newsletter distributed t...ation in this newsletter will help you use our products more effectively in
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Welcome to Novas Notes, a monthly e-mail newsletter distributed to our customers, partners, and friends. We hope
the information in this newsletter will help you use our products more effectively in your design and verification
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Notes

A monthly newsletter for the design verification community
December 2002
In this issue:
Debug Tips
q

Using Verdi to Debug Problems with Data Paths
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Creating Buses from Selected Signals in nWave
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Displaying Mnemonics for Signal Values in nWave
Customer Success Story

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Unisys Tackles 6 Million-Gate Design with Novas
News Coverage

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Verdi Makes EDN Magazine's Top 100 Products
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Novas Systems to Support Verisity Verification Language
q

Expanding Debug Technology
News

q

Verisity, Novas Facilitate Standardization and Extend Debug Interoperability
file:///C|/Documents%20and%20Settings/rvanb/My%2...ewsletter/December%202002/2002-12-Newsletter.htm (1 of 4) [4/8/2003 9:34:59 AM] Newsroom - Welcome to Novas Notes a monthly e-mail newsletter distributed t...ation in this newsletter will help you use our products more effectively in
Debug Tips



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Verdi:
Using Verdi to Debug Problems with Data Paths
When your verification results indicate a likely problem in your design's data paths, you often spend a considerable
amount of time manually tracing backwards through several levels of logic and across many clock cycles to
determine the cause of the problem.
<
Click here for more information
>
Debussy:
Creating Buses from Selected Signals in nWave
It is often useful to create buses from selected signals in the waveform display. nWave supports this capability, as
illustrated in the following example.
<
Click here for more information
>
Displaying Mnemonics for Signal Values in nWave
The nWave window allows you to associate mnemonics with specified signals and signal values. In some cases, this
is done automatically. For example, if you have a Verilog design that contains a state machine, and you use
parameter definitions to specify and assign the state values, then nWave will display the parameter names for the
state variable.
<
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>
Customer Success Story



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Unisys Tackles 6 Million-Gate Design with Novas
Unisys is a worldwide information technology services and solutions company. Its more than 37,000 employees offer
expertise in systems integration, outsourcing, infrastructure, server technology and consulting to help clients, in
more than 100 countries, quickly and efficiently achieve competitive advantage.
<
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>
News Coverage



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file:///C|/Documents%20and%20Settings/rvanb/My%2...ewsletter/December%202002/2002-12-Newsletter.htm (2 of 4) [4/8/2003 9:34:59 AM] Newsroom - Welcome to Novas Notes a monthly e-mail newsletter distributed t...ation in this newsletter will help you use our products more effectively in
EDN Magazine:
Verdi Makes EDN Magazine's Top 100 Products
December 12, 2002: Thousands of new electronic products come along every year. All, no doubt, are useful, and
many are innovative, yet only a relative few generate real excitement. At EDN, we've noted that our readers
respond in a really big way to about a hundred new products each year. Thus was born our year-end feature, the
EDN Top 100 Products. Take a look at what's new this year.
<
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>
EE Design:
Novas Systems to Support Verisity Verification Language
December 2, 2002: Novas Software Inc. said Monday (Dec. 2) that it will increase its support for Verisity Ltd.'s "e"
verification language in Novas' debugging systems, and will participate in "e" language standardization efforts. The
moves come as Novas joins Verisity's LicenseE program, which facilitates third-party support of the language.
<
Click here for more information
>
Electronic Engineering Design:
Expanding Debug Technology
November 13, 2002: As chip size and complexity increases, design verification becomes an increasingly costly and
time-consuming part of product development. Every hour spent trying to figure out how a design is supposed to
work, or why it does not, is an hour that could be better spent on tasks that add more value to the design, increase
its quality and ensure that the schedule is met, such as designing new functions or adding tests to increase
coverage.
<
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>
News



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Press Releases:
Verisity, Novas Facilitate Standardization and Extend Debug
Interoperability
December 2, 2002: Verisity Ltd., the leading supplier of essential technology and methodology for functional
verification, and Novas Software, Inc., the leader in debug systems for complex chip designs, announced that long-
standing Verisity Interoperability Partner (VIP) Novas has joined Verisity's LicenseE program. As a member of
the LicenseE program, Novas will implement support for Verisity's defacto standard e verification language in its
popular debug systems, as well as participate in the e language standardization efforts.
<
Click here for more information
>
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file:///C|/Documents%20and%20Settings/rvanb/My%2...ewsletter/December%202002/2002-12-Newsletter.htm (4 of 4) [4/8/2003 9:34:59 AM] Newsroom - Using Verdi to Debug Problems with Data Paths When your verif...ata paths you often spend a considerable amount of time manually tracing
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Using Verdi to Debug Problems with Data Paths
When your verification results indicate a likely problem in your design's data paths, you often spend a considerable
amount of time manually tracing backwards through several levels of logic and across many clock cycles to
determine the cause of the problem. If you are familiar with the design, you may be able to display the waveforms
for the implicated signals and determine which signal causes the bad data. If you are not familiar with the design,
then the process is much more tedious: Look at the source code to determine the initial set of signals to display,
trace those signals through structure and time to figure out what drives them, add the driving signals to the
waveform display, and so on. It might be necessary to repeat these steps many times before you find the cause of
the bad data. In summary, it requires a lot of manual work and can take a long time.
Verdi provides powerful tracing capabilities that automatically trace through the active logic across multiple cycles to
find the root cause of a transition or value.
For example, assume that you have a signal aluInA that unexpectedly transitions to a value of 55. You can locate
the source of this bad value with a single Verdi command called "trace this value". The following screen shot shows
the results of the "trace this value" command on an example design containing this signal and transition. The
command traces through the active logic across multiple cycles until it reaches signal dataout, which has the first
occurrence of 55 along the active path. In addition to displaying the source of the