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Slot 1 Processor Power Distribution Guidelines 6/8/97 8:56 PM 24333201.DOC
INTEL CONFIDENTIAL
(until publication date)
APPLICATION
NOTE
AP-587
Slot 1 Processor Power
Distribution Guidelines
Order Number: 243332-001
May 1997 6/8/97 8:56 PM 24333201.DOC
INTEL CONFIDENTIAL
(until publication date)
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
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Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Pentium
®
II processor may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
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*Third-party brands and names are the property of their respective owners.
© INTEL CORPORATION 1995, 1996, 1997 AP-587
3
6/8/97 8:56 PM 24333201.DOC
INTEL CONFIDENTIAL
(until publication date)
CONTENTS
PAGE
PAGE
1.0. INTRODUCTION ............................................... 4
1.1. Terminology.................................................... 5
1.2. References..................................................... 5
2.0. TYPICAL POWER DISTRIBUTION.................. 5
3.0. SLOT 1 PROCESSOR POWER
REQUIREMENTS.............................................. 7
3.1. Voltage Tolerance .......................................... 7
3.2. Multiple Voltages ............................................ 7
3.3. Voltage Sequencing ....................................... 8
3.3.1. NON-GTL+ SIGNALS............................. 9
3.3.2. GTL+ SIGNALS .................................... 10
3.3.3. MEMORY SIDE SIGNALS.................... 10
3.3.4. PCI SIDE SIGNALS.............................. 10
3.3.5. CLOCK INPUT...................................... 10
3.3.6. CLOCK RATIO INPUTS ....................... 10
4.0. MEETING THE SLOT 1 PROCESSOR
POWER REQUIREMENTS............................. 12
4.1. Voltage Budgeting ........................................ 12
4.2. Supplying Power .......................................... 13
4.2.1. LOCAL DC-TO-DC CONVERTERS VS.
CENTRALIZED POWER SUPPLY ...... 14
4.2.2. AC VS. DC INPUT VOLTAGE.............. 14
4.2.3. LINEAR REGULATORS VS.
SWITCHING REGULATORS............... 14
4.3. Decoupling Technologies and Transient
Response..................................................... 15
4.3.1. BULK CAPACITANCE.......................... 16
4.3.2. HIGH FREQUENCY DECOUPLING.... 18
4.4. Power Planes or Islands .............................. 19
4.4.1. LOCATION OF HIGH FREQUENCY
DECOUPLING...................................... 21
4.4.2. LOCATION OF BULK DECOUPLING.. 22
4.4.3. IMPEDANCE AND EMISSION
EFFECTS OF POWER ISLANDS........ 22
5.0. THE GTL+ BUS POWER REQUIREMENTS . 22
5.1. Tolerance ..................................................... 23
5.2. Reference Voltage........................................ 23
6.0. MEETING THE GTL+ POWER
REQUIREMENTS............................................ 23
6.1. Generating V
TT
............................................. 23
6.2. Distributing V
TT
............................................. 23
6.3. Generating and Distributing V
REF
................. 24
6.3.1. DISTRIBUTING VREF OR V
TT
............. 24
7.0. RECOMMENDATIONS ................................... 24
7.1. VCC_L2........................................................ 25
7.2. VCC_CORE ................................................. 25
7.2.1. THE MAIN POWER SUPPLY............... 25
7.3. V
TT
............................................................... 25
7.3.1. TERMINATION RESISTORS ............... 27
7.4. V
REF
.............................................................. 27
7.5. Component Models ...................................... 27
8.0. MEASURING TRANSIENTS........................... 28
9.0. EXISTING TECHNOLOGY FOR A SLOT 1
PROCESSOR SYSTEM DESIGN................... 28
9.1. Solutions for VCC_CORE ............................ 28
9.2. Linear Regulators for V
TT
............................. 28
9.3. Termination Resistors .................................. 28
10.0 SLOT 1 PROCESSOR POWER
DISTRIBUTION NETWORK MODELING ...... 28
11.0 RIGHT ANGLE CONNECTOR POWER
DELIVERY CONSIDERATIONS..................... 29
11.1. Right Angle Connector Assumptions ......... 29
11.2. Right Angle Connector Static and
Dynamic Analysis ........................................ 30
11.3. Right Angle Connector Power
Distribution Comparison............................... 31
11.4. Right Angle Connector Typical
Implementation............................................. 31 AP-587
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6/8/97 8:56 PM 24333201.DOC
INTEL CONFIDENTIAL
(until publication date)
1.0.
INTRODUCTION
As computer performance demands increase, new, higher
speed logic with increased density is developed to fulfill
these needs. To reduce their overall power dissipation,
modern microprocessors are being designed with lower
voltage implementations. This in turn requires power
supplies to provide lower voltages with higher current
capability. Because of this, processor power is now
becoming a significant portion of the system design, and
demands special attention. Now more than ever, power
distribution requires careful design practices. Slot 1
processors have unique requirements for voltages
supplied to them. Their bus implementation, called
GTL+, requires a voltage supply of its own.
For most personal computer designs, a power plane with
a mix of high frequency and bulk decoupling capacitors
spread evenly across the system board is a low cost way
to ensure sufficient power distribution. As the current
differences between the low power state and the high
power state increase, the cost of the power distribution
system becomes significant enough to merit careful
calculation. Centralized distribution of power, for
example, may no longer be the most cost effective
solution to power distribution.
Another side effect of lowering voltages of some
components is the existence of multiple voltages within
the system. On a basic Slot 1 processor-based system
board there will be 1.5V for GTL+ termination, 1.8V to
2.8V for the processor, 2.5V for CMOS non-GTL
signals, 3.3V for the chipset and the L2 cache, and 5V for
other components. The possibility that any of these
voltages may come up before another must be taken into
account. This is discussed in Section 3.3.
The reader should be familiar with basic electrical
engineering theory, as the first sections of this document
explain in detail the issues involved in designing a
system with proper power distribution. The last section
includes a specification for a DC-to-DC converter
module.
1.1.
Terminology
Power-Good or PWRGOOD (an active high signal)
indicates that all of the supplies and clocks within the
system stabilize. PWRGOOD should go active some
constant time after 5V, 3.3V and V
CC
P are stable and
should go inactive any time any of these voltages fail
their specifications. The time constant should be set such
that, in a working system, all clocks and other supply
levels have reached a stable condition before
PWRGOOD goes active.
VCC_CORE is the processor cores V
CC
. The
VCC_CORE voltage level varies for different Slot 1
processors. VCC_L2, the Slot 1 processors cache
supply voltage, is always 3.3V.
GTL+ is the technology used for the bus between the
Slot 1 processor and its chipset. The GTL+ bus and the
system bus are therefore synonymous.
1.2.
References
This document contains numerous references to the
Pentium
®
II Processor at 233 MHz, 266 MHz and
300 MHz datasheet (Order Number 243335).
2.0.
TYPICAL POWER
DISTRIBUTION
Power distribution is generally thought of as getting
power to the parts that need it. Most digital designers
typically begin by assuming that an ideal supply will be
provided, and plan their schematics with little thought to
power distribution until the end. The printed circuit board
(PCB) designers attempt to create the ideal supply with
two power planes in the PCB or by using large width
traces to distribute power. High frequency noise created
when logic gates switch is controlled with high
fr