k MOSFETs
Gate Sizing: FinFETs vs 32nm Bulk MOSFETs Brian Swahn
and
Soha Hassoun
Tufts University
Medford, MA 02155
swahn@ece.tufts.edu, soha@cs.tufts.edu
ABSTRACT
FinFET devices promise to replace traditional MOSFETs because
of superior ability in controlling leakage and minimizing short chan-
nel effects while delivering a strong drive current. We investigate
in this paper gate sizing of nFET devices, and we provide a com-
parison with 32nm bulk CMOS. Wider nFET devices are built
utilizing multiple parallel ns between the source and drain. In-
dependent gating of the nFETs double gates allows signicant
reduction in leakage current. We perform temperature-aware cir-
cuit optimization by modeling delay using temperature-dependent
parameters, and by imposing constraints that limit the maximum
allowable number of parallel ns. We show that nFET circuits are
superior in performance and produce less static power when com-
pared to 32nm circuits.
Categories and Subject Descriptors:
B.7.1 [Integrated Circuits]:
Types and Design Styles
General Terms:
Design
Keywords:
FinFET, thermal modeling, gate sizing
1.
INTRODUCTION
The scaling of the MOSFET transistor has delivered astronomi-
cal increases in transistor density and performance, leading to more
chip functionality at higher speeds. The main roadblock to contin-
ued success is the leakage phenomenon. Increased leakage stems
from decreased oxide thicknesses, higher substrate dopings, and
decreased channel lengths. A lowered threshold voltage to ob-
tain better performance at lowered operating voltages further ex-
acerbates the leakage problem. Moreover, the continued-shrinking
proximity of the source and drain reduces the effective control of
the gate over the channel, accentuating DIBL, drain-induced-barrier
lowering. The ITRS predicts that static power dissipation per de-
vice will surpass the dynamic power dissipation by 2007.
To reduce leakage while scaling performance, the 2003 ITRS
predicts using strained silicon channels, ultra-thin single-gate FETs,
and metallic gates. The ITRS predicts ultimately moving towards
double-gate (and multi-gate) devices. From a circuit perspective,
the double-gate devices operate in a manner similar to MOSFETs. This research was supported by NSF grant CCF-0429921, and a
gift from the Altera Corp.
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When a potential larger than the threshold voltage, V
T
, is applied
between the gates of the DG device and source, current ows from
the drain to the source. The double gates, however, allows modu-
lating the channel from two sides instead of one. The two gates to-
gether strongly inuence the channel potential, combating the drain
impact, and leading to the better ability to shut off the channel cur-
rent. DIBL is thus reduced, and the swing is improved.
While several double-gate transistor variations have been inves-
tigated, recent research efforts have focused on nFETs, illustrated
in Figure 1(a). The nFET, originally dubbed as the folded-channel
MOSFET [10], consists of a narrow vertical n that sticks up from
the wafer surface (z-direction). Source and drain terminals are built
at opposite ends of the n. The gate, whose width is twice the n
height, drapes over the n. The current ow in the channel is paral-
lel to the plane of the wafer, and thus the label quasi-planar despite
what appears to be a non-planar n. Other multi-gated planar and
non-planar devices have been proposed, however, nFETs, are a
likely contender because of cost-effective manufacturing, the natu-
ral alignment of the double gate, and routability of the gate.
Figure 1(a) illustrates key geometric parameters for a nFET.
The distance between the source and drain is referred to as the gate
length, L
gate
. The n height, H
f in
, is uniform for all ns on chip.
A larger height complicates processing and causes defects. The
oxide thickness between the side gates and the n is t
ox
. The ox-
ide thickness between the top gate and the n is t
ox
top
. W
f in
is
the n thickness. Fin engineering (balancing height, n thickness,
oxide thickness, and channel length) is essential in minimizing the
leakage current, I
off
, and maximizing the on current, I
on
.
We investigate in this paper issues in nFET sizing and inde-
pendent gate biasing of the front and back gates while considering
thermal constraints. FinFET sizing is challenging because wider
devices are created using multiple ns. Device-width quantization
thus must be considered [3]. FinFET sizing then consists of nding
the optimal number of parallel n for each gate in the circuit. In-
dependent biasing of one of the nFET gates provides lower leak-
age yet performance is affected. Independent biasing must thus
be judiciously used. We use an NLP-based heuristic to solve the
sizing problem, and we provide a detailed comparison with 32nm
bulk CMOS devices. For this investigation, we design our base
device to have the following characteristics, typical of recent man-
ufactured nFETs: L
gate
= 45<i>nm ; H
f in
= 65<i>nm ; W
f in
= 10<i>nm;
t
ox
= 1.6<i>nm. We use the UFDG SPICE models [8] to generate our
nFET data and the 32nm Predictive Technology Modeling (PTM)
models [14, 17] to generate our 32nm bulk data.
We begin with a discussion of issues of sizing nFETs vs 32nm
devices. We then present the problem formulation and the solution.
We conclude with experimental results.
2.
ISSUES IN SIZING: FINFETS VS 32NM
2.1
Discrete vs. Continuous Sizing
The width of a nFET (i.e. the width of the area controlled by the
gates), is dened as: W
gate
= 2 × H
f in
. Wider nFETs are formed (a) FinFET device.
(b) Multi-n device [3].
Figure 1: FinFET device geometries.
by draping the gate across multiple ns between the source and
drain region, as shown in Figure 1(b) [3]. These ns are tightly laid
out to minimize area and gate resistance. Fin sizing is then a dis-
crete optimization problem, with an n-n device delivering about n
times the current delivered by a single-n device, and introducing
n times the load due to a single-n device.
For traditional MOSFETs, the issue of discrete vs. continuous
transistor sizing has been thoroughly investigated. While library
gate sizes are discrete, continuous optimization techniques are pre-
sumably faster and they are often applied. The solution is then
converted to discrete sizes. Provided a rich set of library, the per-
formance impact of using this method is within 2%-7% or less [7,9]
of discrete sizing. Furthermore, optimal gate sizes found using con-
tinuous techniques can be constructed by combining gates from a
standard library with high accuracy [9]. As we will see in Sec-
tion 3, we propose an approximating heuristic to solve the nFET
sizing problem while using a non-linear programming formulation
and solver to nd optimal sizes for the devices in the 32nm circuits.
1.0E-12
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Id [A]
Vgs [V]
32nm Bulk NMOS
FinFET NMOS - Wfin = 10nm
FinFET NMOS - Wfin = 20nm
Figure 2:
FinFET and 32nm I-V characteristics.
2.2
I
on
and
I
o f f
Figure 2 illustrates the on and off currents for a minimally sized
n-type 32nm device vs. an n-type nFET (W
f in
= 10<i>nm). FinFETs
provide more on current than the 32nm devices, resulting in faster
switching times. Bulk CMOS has several leakage mechanisms:
subthreshold leakage, gate leakage, reverse-biased junction, band-
to-band tunneling (BTBT), and gate-induced drain leakage [13]. In
a nFET, there are two leakage mechanisms: the subthreshold cur-
rent and gate leakage [2]. Figure 2 also shows I
on
and I
off
for dif-
ferent n thicknesses; both I
on
and I
off
increase as the n thickness
increases. The increase in I
on
is due to a reduction in n and para-
sitic source/drain resistances, while decreased gate control over the
channel causes an increase in I
off
.
2.3
Gate vs. Body Biasing
For bulk CMOS, energy reduction is achieved via adaptive body
biasing (ABB) and multiple-threshold MOSFETs. ABB research
showed that adjusting the body voltage is an effective method for
post-silicon tuning to reduce V
T
variability under process variation,
reducing leakage current and thus energy, and tripling the accepted
die count in the highest frequency bin [16]. ABB was shown to be
most effective when combined with adaptive supply voltage con-
trol.
FinFETs can provide some operating bias similar to that achieved
via ABB. The front and back gates of a nFET can be made electri-
cally independent (no top oxide is deposited). By applying differ-
ent potentials to the gates, both the threshold voltage of the device
and the leakage current can be changed. Fried and his colleagues
describe such a device [6]. The independent biasing of a multi-n
device slows the device and results in added net area to allow for
routing the two gate signals.
2.4
Temperature Dependence
While nFETs provide excellent electrostatic characteristics, they
suffer from signicant self-heating. The small and conned dimen-
sions of the n reduce the thermal conductivity (which increases
the thermal resistance) of the dev