cellspacing=0 width=100%>Yahoo! is not affiliated with the authors of this page or responsible for its content.
"UCC3895 Advanced Phase Controller Evaluation Board" User Guide
SLUU069A - September 2000
1
UCC3895 Phase Shift PWM Controller
EVM Kit Setup and Usage
Power Supply Control Products
1
Introduction
The UCC3895 evaluation board is a 48-V input dc-to-dc converter providing 3.3 V at 15 A. It also
provides 1500-V isolation between the primary and secondary portions of the circuit. This users
guide provides the test setup and component details needed to evaluate the UCC3895
evaluation board, along with some operational waveforms.
This evaluation board uses the UCC3895 advanced phase shift PWM controller to implement
control of a full-bridge power stage by phase-shifting the switching of one half-bridge with
respect to the other half-bridge. The circuit operates at a fixed frequency using peak current
mode control, yet promotes zero voltage switching (ZVS) over a significant portion of the
converter load range. ZVS is achieved by using the converters parasitic capacitance, leakage
inductance, and a small discrete inductor in series with the primary winding. Additional
information on the full-bridge phase-shifting technique and the current-doubler rectifier can be
found in references [1] - [3].
This evaluation board is intended to provide an introduction to phase-shifting full-bridge power
converters at a safe input voltage and power level. It is recognized that 50 W is below the typical
application level of a full-bridge power supply. This topology can be used from a few hundred
watts to several kilowatts with the same basic circuit configuration.
1.1
Features
The UCC3895 phase-shift PWM controller includes: Programmable output turnon delay Adaptive delay set Bidirectional oscillator synchronization Capability for voltage mode or current mode control Programmable softstart and chip disable via a single pin 0% to 100% duty cycle control 7-MHz error amplifier Operation to 1 MHz Low active current consumption (5 mA typical @ 500 kHz) Very low current consumption during undervoltage lockout (150
�
A typical) SLUU069A
2
UCC3895 Phase Shift PWM Controller
1.2
Description
The UCC3895 provides the logic and drive signals to control the full-bridge phase shifted power
supply, maintaining the functionality of the UC3875/6/7/8 and the UC3879. However, the
UCC3895 improves on the previous phase shift controller families by adding features such as
enhanced control logic, adaptive delay set, and shutdown capability. Since it is built in
BCDMOS, it operates with dramatically less supply current than its bipolar counterparts.
2
Schematic
A schematic of the UCC3895 evaluation board is shown in Figure 1. Terminal J2 is the input
voltage source, J3 takes an external bias supply, and the output is taken from J1.
A quick overview of the primary circuitry on the left-hand portion of the schematic shows the
full-bridge power section in the center comprised of MOFETs Q1-Q4. The control signals are
provided by U1, the UCC3895, with its accompanying circuitry. Current transformer T2 senses
the primary current and provides information to the controller. PWM outputs OUTA-OUTD are
buffered through driver ICs, U5 and U7, and connected to the power switching devices through
gate drive transformers T3 and T4. Power is delivered to the secondary through power
transformer T1.
The secondary portion of the circuit is shown on the right-hand side, and is fed from the single
secondary winding of T1. This rectifier is comprised of diodes D9 and D10, output chokes L2
and L3, and output capacitors C15 and C16. The output voltage is sensed through the R17-R18
divider, and a TL431 is used as an error amplifier to feed back an error signal through
optocoupler U3. The onboard amplifier in the UCC3895 is configured as a voltage follower in this
application. SLUU069A
3
UCC3895 Phase Shift PWM Controller
UDG99127
1IN
TP25
TP24
TP23
TP22
TP21
TP20
TP19
TP18
TP17
TP16
TP15
TP14
TP13
TP12
TP1
1
TP10
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP1
C13
J1
U6
TL431
J3
J2
C1
22 nF
C2
100 pF
C3
C4
330 pF
Q9
MMBT3904
EA+
EA+
D8
BAR74
D7
BAR74
7
8
6
4
T2
C8
4.7 nF
D1
BAR74
D6
1N4738A
C17
6.8 nF
C14
3.3 nF
C12
C1
1
+
C10
100 V
C9
47 nF
C7
C6
+ C5
C31
4.7 nF
C30
4.7 nF
+
C16
+
C15
L3
L2
HS3
Q3
HS6
D10
32CTQ030
HS5
D9
32CTQ030
L1
1
2
3
4
5
6
T4
1
2
3
4
5
6
T3
HS1
Q1
HS2
Q2
HS4
Q4
U5
1
2
5
4
6
U3
8
1
6
VCC
3
GND
7
1OUT
4
2IN
2
5
2OUT
U5
8
1
6
VCC
3 GND
7
1OUT
4
2IN
2
1IN
5
2OUT
U7
1 EA 2
EAO
3
RAMP
4
REF
5
GND
6
SYNC
7
CT
8
RT
9
DELAB
10
DELCD
11
ADS
12
CS
13
OUTD
14
OUTC
15
VCC
16
PGND
17
OUTB
18
OUT
A
19
SS/SD
20
EA+
U1
1
2
5
4
3
T1
R1
510
R2
2 k
R3
2 k
R4
69.8 k
R5
2.4 k
R6
2.4 k
R7
R8
10
R9
20
R10
510
R20
500
R19
20 k
R18
8.66 k
R17
2.8 k
R16
274
R15
100
2 W
R37
10
2 W
R36
10
R32
5 k
R34
4.7
R35
4.7
R33
5 k
R31
5 k
R30
5 k
0.1

�
F
2200
�
F
2.2
�
H
2200
�
F
0.1
�
F
2.2
�
H
470
�
F
0.47
�
H
0.1
�
F
0.1
�
F
1
�
F
1
�
F
47
�
F
open
Figure 1. Evaluation Board Schematic SLUU069A
4
UCC3895 Phase Shift PWM Controller
3
Circuit performance
This circuit has been built and evaluated in the laboratory. Figure 2 shows the pertinent
waveforms to demonstrate zero voltage switching at the rated load of 15 A. Note that the gate
drive swings positive and negative 10 V around ground, and is still negative when the
drain-source voltage of Q2 reaches 0 V. Then, the gate-source voltage goes positive to turn Q2
ON. At loads below 10 A, the circuit loses ZVS. References [1] and [2] provide much detail on
the component relationships that affect the ZVS operation. Note that the plateau visible in the
V
GS
, Q2 waveform in Figure 2 is from the turnoff of Q1, the other MOSFET driven by the same
gate drive transformer.

Figure 2. Zero Voltage Switching ZVS of Q2
At a load current of 15 A, the circuit has an efficiency of 76.8% with Schottky rectifiers. These
rectifiers were used to keep the complexity of this EVM low in order to simplify the evaluation of
the UCC3895 control IC. In the lab, each Schottky was replaced with a single control-driven
synchronous-rectifier (SR) MOSFET and the efficiency was measured to be 83% at 15 A.
Multiple SR MOSFETs and suitably sized magnetics could be used to extend the power range to
hundreds of watts with good efficiency. Note that the full bridge does suffer a penalty due to the
necessity of driving four devices; this is mitigated as the power level increases.
The study of the EVM efficiency led the author to find that the primary-side gate-drive
transformers are being pushed to the limits of acceptable operation. An application at 200-kHz
with a constant 50% duty cycle causes the transformers to run at the edge of a soft saturation
characteristic in normal operation. This causes some undesired losses in the core material and
drivers ICs. This component would be effective at 400 kHz500 kHz but should be replaced in
this 200 kHz application. Possible solutions include increasing the core cross-sectional area in
the gate-drive transformer or replacing the gatedrive transformer and driver IC with a high-speed
half-bridge driver IC. SLUU069A
5
UCC3895 Phase Shift PWM Controller
4
Test points
Twenty-five testpoints have been provided to monitor the significant voltage waveforms in the
circuit. Their locations are given in Table 1.
Test Point Designations and Locations
TEST POINT
LOCATION
TP1
U1 pin 3, RAMP
TP2
U1 pin 7, C
T
TP3
U1 pin 20, EA+
TP4
U1 pin 14, OUTC
TP5
U1 pin 13, OUTD
TP6
U5 pin 7, driverA
TP7
U1 pin 17, OUTB
TP8
U1 pin 18, OUTA
TP9
U1 pin 5, control GND
TP10
U1 pin 12, CS
TP11
T2 pin 6, CT signal
TP12
Q1 source, Q2 drain
TP13
Power GND
TP14
U7 pin 5, driverD
TP15
U7 pin 7, driverC
TP16
U6 pin 3, TL431 cathode
TP17
Q3 source, Q4 drain
TP18
T1 pin 5,
transformer secondary
TP19
V
IN
()
TP20
V
IN
(+)
TP21
U6 pin 1,
TL431 reference
TP22
V
OUT
()
TP23
V
OUT
(+)
TP24
U6 pin 2,
secondary common
TP25
Q2, gate SLUU069A
6
UCC3895 Phase Shift PWM Controller
5
Test setup
Figure 2 shows the basic lab configuration needed to power up the UCC3895 EVM.
UUT
LOAD SELECTABLE
3.3 V @ 15 A
or
3.3 V @ 1.5 A
V
(0 V 50 V)
VBIAS
(012 V)
A1
J
3
+ J
2
+ J
1
+
+
V1
TP23
TP22
+ + FAN
IN
Figure 3. Basic Lab Configuration
5.1
Logic Power Required (V
BIAS
)
An external bias supply should be applied to J3 to bring the control circuitry alive before input
power is applied. V
BIAS
should be raised above the UVLO threshold (11 V) of the UC3895, and
then set at 10.5 V for optimal efficiency. With the J3 bias applied the control and switching
circuitry can be checked from the UCC3895 outputs out to the gates of the switching MOSFETs
Q1Q4.
5.2
Input Source (V
IN
)
The input voltage source applied to J2 should be capable of delivering 2 A of current to allow
operation at full load. With an input of 48 V and an efficiency of approximately 75% the
evaluation board draws 1.4 A with a 50-W load. Wire of 22 gauge (or larger wire diameter) can
be used to make the input connections.
5.3
Output Load
The output connections to J1 should be made with (2) parallel 16 gauge wires, or larger, for both
the + output and the return to the load. Paralleled resistors or an electronic load can be used,
with the latter enabling easier output current measurements. Using (2) parallel 16 gauge wires to
run 2 feet to a load introduces a voltage drop over 100 mV, so remember to make all output
vo