br>Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP820xHDM Overvoltage Protectors
TISP8200HDM BUFFERED P-GATE SCR DUAL
TISP8201HDM BUFFERED N-GATE SCR DUAL
COMPLEMENTARY BUFFERED-GATE SCRS
FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION
TISP8200HDM 8-SOIC (210 mil) Package (Top View)
*RoHS COMPLIANT
High Performance Protection for SLICs with +ve & -ve
Battery Supplies
TISP8200HDM Negative Overvoltage Protector
Wide -20 to -110 V Programming Range
Low +15 mA Max. Gate Triggering Current
High -150 mA Min. Holding Current
TISP8201HDM Positive Overvoltage Protector
Wide +20 to +110 V Programming Range
Low -15 mA Max. Gate Triggering Current
+20 mA Min. Holding Current
Rated for International Surge Wave Shapes
Wave Shape
Standard
I
PPSM
A
2/10
GR-1089-CORE
500
10/700
ITU-T K.20/21/45
150
10/1000
GR-1089-CORE
100
MD-8SOIC(210)-007-a
NC - No internal connection
Terminal typical application names shown in parenthesis
1
2
3
4
5
6
7
8
K1
A
A
K2
G
K1
K2
NC
(Tip)
(Ground)
(Ground)
(Ring)
(-V
(BAT)
)
(Tip)
(Ring)
TISP8200HDM Device Symbol
SD-TISP8-001-a
G
K1
K1
K2
K2
A
A
Circuit Application Diagram
TISP8201HDM 8-SOIC (210 mil) Package (Top View)
MD-8SOIC(210)-008-a
NC - No internal connection
Terminal typical application names shown in parenthesis
1
2
3
4
5
6
7
8
A1
K
K
A2
G
A1
A2
NC
(Tip)
(Ground)
(Ground)
(Ring)
(+V
(BAT)
)
(Tip)
(Ring)
TISP8201HDM Device Symbol
SD-TISP8-002-a
G
A1
A1
A2
A2
K
K
- V
BAT
SLIC
PROTECTION
TISP8201HDM
AI-TISP8-002-b
Tip
Ring
C2
220 nF
+V
BAT
C1
220 nF
TISP8200HDM

..................................................UL Recognized Component OCTOBER 2005 REVISED MAY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP820xHDM Overvoltage Protectors
Description
The TISP8200HDM/TISP8201HDM combination has been designed to protect dual polarity supply rail monolithic SLICs (Subscriber Line
Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. Protection against negative
overvoltages is given by the TISP8200HDM. Protection against positive overvoltages is given by the TISP8201HDM. Both parts are in 8-SOIC
(210 mil) surface mount packages.
The TISP8200HDM has an array of two buffered P-gate SCRs with a common anode connection. Each SCR cathode and gate has a separate
terminal connection. The NPN buffer transistors reduce the gate supply current. In use, the cathodes of the TISP8200HDM SCRs are connected
to the two conductors of the POTS line. The gates are connected to the appropriate negative voltage battery feed of the SLIC driving the line
conductor pair, so that the TISP8200HDM protection voltage tracks the SLIC negative supply voltage. The anode of the TISP8200HDM is
connected to the SLIC common. Negative overvoltages are initially clipped close to the SLIC negative supply by emitter follower action of the
NPN buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the
overvoltage subsides the high holding current of the SCR prevents d.c. latchup.
The TISP8201HDM has an array of two buffered N-gate SCRs with a common cathode connection. Each SCR anode and gate has a separate
terminal connection. The PNP buffer transistors reduce the gate supply current. In use, the anodes of the TISP8201HDM SCRs are connected
to the two conductors of the POTS line. The gates are connected to the appropriate positive voltage battery feed of the SLIC driving that line
pair, so that the TISP8201HDM protection voltage tracks the SLIC positive supply voltage. The cathode of the TISP8201HDM is connected to
the SLIC common. Positive overvoltages are initially clipped close to the SLIC positive supply by emitter follower action of the PNP buffer
transistor. If sufficient clipping current flows the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage sub-
sides the SLIC pulls the conductor voltage down to its normal negative value and this commutates the conducting SCR into a reverse biased
condition.
How to Order
Device
Package
Carrier
Order As
Marking Code
Standard Quantity
TISP8200HDM
8-SOIC (210 mil)
Embossed Tape Reeled
TISP8200HDMR-S
8200H
2000
H
1
0
2
8
S
-
R
M
D
H
1
0
2
8
P
S
I
T
M
D
H
1
0
2
8
P
S
I
T
t
i
n
U
e
u
l
a
V
l
o
b
m
y
S
g
n
i
t
a
R
Repetitive peak off-state voltage, V
GK
V
0

=

DRM
-120
V
Repetitive peak reverse voltage, V
GA
V
V

0
7
-

=

RRM
120
Non-repetitive peak impulse current (see Notes 1, 2 and 3)
2/10 µs (Telcordia GR-1089-CORE, 2/10 µs voltage wave shape)
5/310 µs (ITU-T K.44, 10/700 µs voltage wave shape used in K.20/21/45)
10/1000 µs (Telcordia GR-1089-CORE, 10/1000 µs voltage wave shape)
I
PPSM
-500
-150
-100
A
Non-repetitive peak on-state current, 50/60 Hz (see Notes 1, 2, 3 and 4)
10 ms
1 s
7 s
900 s
I
TSM
60
14
7
3.5
A
Junction temperature
T
J
-55 to +150
°C
Storage temperature range
T
stg
-65 to +150
°C
NOTES: 1. Initially the device must be in thermal equilibrium with T
J
= 25 °C. The surge may be repeated after the device returns to its initial
conditions.
2. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair.
3. Rated currents only apply if pins 1 & 8 (K1,Tip) are connected together, pins 4 & 5 (K2, Ring) are connected together and pins
6 & 7 (A, Ground) are connected together.
4. These non-repetitive rated terminal currents are for the TISP8200HDM and TISP8201HDM together. Device (A)-term inal positive
current values are conducted by the TISP8201HDM and (K)-terminal negative current values by the TISP8200HDM.
TISP8200HDM Absolute Maximum Ratings, T
A
= 25 °C (Unless Otherwise Noted) OCTOBER 2005 REVISED MAY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP820xHDM Overvoltage Protectors
TISP8201HDM Absolute Maximum Ratings, T
A
= 25 °C (Unless Otherwise Noted)
t
i
n
U
e
u
l
a
V
l
o
b
m
y
S
g
n
i
t
a
R
Repetitive peak off-state voltage, V
GA
V
0

=

DRM
120
V
Repetitive peak reverse voltage, V
GK
V
V

0
7

=

RRM
-120
Non-repetitive peak impulse current (see Notes 5, 6 and 7)
2/10 µs (Telcordia GR-1089-CORE, 2/10 µs voltage wave shape)
5/310 µs (ITU-T K.44, 10/700 µs voltage wave shape used in K.20/21/45)
10/1000 µs (Telcordia GR-1089-CORE, 10/1000 µs voltage wave shape)
I
PPSM
500
150
100
A
Non-repetitive peak on-state current, 50/60 Hz (see Notes 5, 6, 7 and 8)
10 ms
1 s
7 s
900 s
I
TSM
60
14
7
3.5
A
Junction temperature
T
J
-55 to +150
°C
Storage temperature range
T
stg
-65 to +150
°C
NOTES: 5. Initially the device must be in thermal equilibrium with T
J
= 25 °C. The surge may be repeated after the device returns to its initial
conditions.
6. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair.
7. Rated currents only apply if pins 1 & 8 (A1, Tip) are connected together, pins 4 & 5 (A2, Ring) are connected together and pins
6 & 7 (K, Ground) are connected together.
8. These non-repetitive rated terminal currents are for the TISP8200HDM and TISP8201HDM together. Device (A)-term inal positive
current values are conducted by the TISP8201HDM and (K)-terminal negative current values by the TISP8200HDM.
t
i
n
U
x
a
M
p
y
T
n
i
M
3

e
r
u
g
i
F

e
e
S
C1, C2 Gate decoupling capacitor
220
nF
t
i
d
n
o
C

t
s
e
T
r
e
t
e
m
a
r
a
P
t
i
n
U
x
a
M
p
y
T
n
i
M
s
n
o
i
I
DRM
Repetitive peak off-state current
V
D
= V
DRM
, V
GK
A
µ
5
-
0

=

I
RRM
Repetitive peak reverse current
V
R
= V
RRM
, V
GA
A
µ
5
V

0
7
-

=

V
(BO)
Breakover voltage
dv/dt = -250 V/ms, R
SOURCE
= 300
V
GA
V
2
8
-
V

0
8
-

=

V
(BO)
Impulse breakover voltage
dv/dt -1000 V/µs, Linear voltage ramp,
Maximum ramp value = -500 V
di/dt = -20 A/µs, Linear current ramp,
Maximum ramp value = -10 A
V
GA
= -80 V
-90
V
I
H
Holding current
(I
K
) I
T
= -1 A, di/dt = 1 A/ms, V
GA
A
m
0
5
1
-
V

0
8
-

=

I
GT
Gate trigger current
(I
K
) I
T
= -5 A, t
p(g)
20 µs, V
GA
A
m
5
1
V

0
8
-

=

C
O
Off-state capacitance
f = 1 MHz, V
d
= 1 V rms, Gate open
V
D
= -2 V
65
pF
V
D
= -50 V
30
Recommended Operating Conditions
TISP8200HDM Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted) OCTOBER 2005 REVISED MAY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP820xHDM Overvoltage Protectors
TISP8201HDM Electrical Characteristics, TA = 25 °C (Unless Otherwise Noted)
t
i
d
n
o
C

t
s
e
T
r
e
t
e
m
a
r
a
P
t
i
n
U
x
a
M
p
y
T
n
i
M
s
n
o
i
I
DRM
Repetitive peak off-state current
V
D
= V
DRM
, V
GA
A
µ
5
0

=

I
RRM
Repetitive peak reverse current
V
R
= V
RRM
, V
GK
A
µ
5
-
V

0
7

=

V
(BO)
Breakover voltage
dv/dt = 250 V/ms, R
SOURCE
= 300
V
GK
V
2
8
V

0
8

=

V
(BO)
Impulse breakover voltage
dv/dt 1000 V/µs, Linear voltage ramp,
Maximum ramp value = 500 V
di/dt = 20 A/µs, Linear current ramp,
Maximum ramp value = 10 A
V
GK
= 80 V
90
V
I
H
Holding current
(I
A
) I
T
= 1 A, di/dt = -1 A/ms, V
GK
A
m
0
2
V

0
8

=

I
GT
Gate trigger current
(I
A
) I
T
= 5 A, t
p(g)
20 µs, V
GK
A
m
5
1
-
V

0
8

=

C
O
Off-state capacitance
f = 1 MHz, V
d
= 1 V rms, Gate open
V
D
= 2 V
50
pF
V
D
= 50 V
30
Thermal Characteristics
t
i
d
n
o
C

t
s
e
T
r
e
t
e
m
a
r
a
P
t
i
n
U
x
a
M
p
y
T
n
i
M
s
n
o
i
R
JA
Junction to ambient thermal resistance
EIA/JESD51-7 PCB, EIA/JESD51-2 Environment, P