olumn lines in an AMLCD introduces significant
propagation delays to their respective addressing signals. The
row signal delay is conventionally accommodated by shortening
the row select time, which requires lower TFT on-resistance to
provide adequate charging ratios of the pixels. We present a new
approach to column driving which results in a much-improved
pixel-charging ratio. The benefit is of particular interest to large-
area, high-resolution, wide-aspect-ratio, LCD TVs.
1.0
Background and History
The line-by-line, scan-and-hold feature of the active-matrix, TFT
LCD means that each sub-pixel is operated as a sample-and-hold
circuit. That is, when a row line is selected, all the sub-pixels on
that row begin to acquire the voltage on their respective column
lines. The sub-pixel charging time is designed to allow the sub-
pixel voltage to equalize with the column line voltage before the
end of the line time. At the end of the line time, the row signal
falls latching this acquired voltage until the same line is addressed
in the following frame.
In practice, it takes time for the row signal to propagate from the
row driver, through the row line, to the other side of the panel.
This is because the row line is electrically a distributed RC line.
The propagation delay of the row signal through the RC line
means that the latching of the sub-pixel on the far side of the
panel will be slightly delayed from the latching of the sub-pixel
near the row driver. This delay time is typically designed to be in
the range of 1 to 3 microseconds.
In the conventional system, the column drivers transition from the
voltage for the selected line to the voltage for the next line
simultaneously, from one side of the panel to the other. That is,
all column driver outputs on all the column drivers change at the
same time. The 1 to 3 microsecond delay of the row line signal
means that the column line signals must be held valid until the
falling edge of the row signal reaches the far side of the panel. To
prevent the column line voltages from changing before the row
signal reaches the other end, the row pulse is shortened by an
amount equal to the propagation time across the panel.
To shorten the row pulse, the row drivers provide a global output
enable signal (OE) which when inactive forces all of the outputs
to the de-select state (low). Since only one output is active at a
time, this OE signal can be used to force a shortened row pulse
signal on every line. In practice the electronic design engineer
will adjust the width of the OE signal to tune the driving
waveform to the particular panel designs propagation
characteristics. Figure 1 shows how the row pulse signal width is
shortened to allow for propagation of the falling edge to the far
end of the line. Figure 2 shows the general concept of the OE
signal. It should be noted that whenever OE is de-asserted, no
row driver outputs are active. Therefore the portion of line time
in which OE is de-asserted (low) is in a large sense a measure of
how much of the row time is actually used for propagating the
row signal rather than for charging the sub-pixel. Clearly we want
to maximize the portion of the line time used to charge the sub-
pixel [2].

TFT TURN
OFF
THRESHOLD
row signal
waveform at far
end of row line
row signal
waveform near
the row line
1 line time
column
line signal
row driver output enable signal
TFT TURN
OFF
THRESHOLD
row signal
waveform at far
end of row line
row signal
waveform near
the row line
1 line time
column
line signal
row driver output enable signal

Figure 1. The falling edge of the Row Signal takes time to
propagate from the row driver to the far end of the row line. This
requires the row pulse width to be shortened to assure that the
signal reaches the far end of the row line before the column line
data switches to the next lines voltage.

Line
Time
N
Line
Time
N+1
Line
Time
N+2
Line
Time
N+3
OE
Row N
Row N+1
Row N+2
Row N+3
Line
Time
N
Line
Time
N+1
Line
Time
N+2
Line
Time
N+3
OE
Row N
Row N+1
Row N+2
Row N+3

Figure 2. Timing of the row signals OE signal









ISSN/0004-0966X/04/3501-0
280-$1.00+.00 © 2004 SID
280 SID 04 DIGEST P-16 / S. H. Kim

2.0 Alternate
Approach
Horizontal Line Delay Compensation (H-LDC) is an alternate
method to compensate for the propagation delay of the row signal.
Rather than transitioning all the outputs of all the column drivers
simultaneously, each output of each column driver is delayed an
amount that matches the propagating edge of the row signal as it
passes that output. In other words, each column driver time
staggers their output transitions, in step with the row signal
propagation, to assure that the column driver changes states
immediately after the row signal falls. This means that since no
output must wait for the gate signal to propagate, whether the
column driver output is near or far from the row driver, there is
additional time to charge each pixel.
Notice in Figure 1 how the column driver signals near the row
driver remain unchanged well after the row signal falls (red line).
From the perspective of these column driver outputs, those near
the row driver, the row driver signal could fall much later and
provide additional time to charge the sub-pixel.
Figure 3 compares the driving waveforms of the conventional
method for the row signal propagation compensation with the
improved H-LDC method. Each of the three Figures, 3a, 3b and
3c have a common datum, the time at which the row driver signal
begins to transition from low to high. This defines the beginning
of a new line. In other words, notice that the time at which the
row signal begins to transition from low to high is the same in
Figures 3a, 3b and 3c. The row signals in Figure 3b and 3c are
identically the same, the only differ in which end of the line is
highlighted. Notice that the total on-time of the row select line is
shorter in Figure 3a than it is in Figures 3b and 3c. This is a key
benefit of H-LDC. The only difference between Figure 3b and 3c
is when the column line signal transitions. In the conventional
approach each column driver output must transition in unison with
all the others. In H-LDC, each output of each column driver
transitions independently and progressively later than the previous
output (i.e. the one nearer the row line).
2.1 Implementation
One of the enabling technologies used to simplify the
implementation of H-LDC is the PPDS architecture now being
introduced by National Semiconductor into the market [1].
In the PPDS system, the Timing Controller communicates to each
Column Driver separately through a single, point-to-point link
rather than across a global, multi-drop bus. In addition to the
video data sent across this link from the Timing Controller to the
Column Driver, this link carries specific column driver control
commands in a header of the packet of data that is sent with each
new line.
With H-LDC the Column Driver outputs are divided into small
banks which while they operate synchronously as a group, are
small enough to approximate operation as individual outputs. One
of two control parameters sent to each column driver to
implement H-LDC is the number of PPDS link clock cycles to
wait following the global, start-of-next-line signal before
transitioning any output. The other parameter is the number link
cycles to wait before starting each successive bank of grouped
outputs. To program the column drivers in the PPDS system
for H-LDC, the column driver nearest the row driver is told to
wait 0 clock cycles following the new row strobe signal called
LOAD. In addition, it is told to start the transition of each
separate bank of outputs delayed from the previous bank by N
clock cycles. Assuming that the column driver outputs are
grouped into 8 separate banks, the next column driver away from
the row driver is programmed with a start time of 8N clocks
following the same global LOAD signal as well as a step size of
M clock cycles. The remaining column drivers are programmed
likewise thereby allowing each output of each column driver to
transition approximately in step with the exact delay of the row
signal falling edge at that outputs position along the row line.

TFT TURN
OFF
THRESHOLD
row signal
waveform at far
end of row line
row signal
waveform near
the row line
1 line time
All column
line signals
row driver OE signal
TFT TURN
OFF
THRESHOLD
1 line time
Shortened OE
TFT TURN
OFF
THRESHOLD
1 line time
row driver OE signal
Conventional Method Shortened Row Pulse
H-LDC Method Skewed Column Signal
Column line
signal near
row driver
Column line
signal at far
end of row
3a.
3b.
3c.
TFT TURN
OFF
THRESHOLD
row signal
waveform at far
end of row line
row signal
waveform near
the row line
1 line time
All column
line signals
row driver OE signal
TFT TURN
OFF
THRESHOLD
1 line time
Shortened OE
TFT TURN
OFF
THRESHOLD
1 line time
row driver OE signal
Conventional Method Shortened Row Pulse
H-LDC Method Skewed Column Signal
Column line
signal near
row driver
Column line
signal at far
end of row
3a.
3b.
3c.

Figure 3. Conventional shortened row pulse v.s. H-LDC signals.
The conventional approach is shown in 3a. H-LDC signals near
the row driver and far from the row driver are shown in 3b and 3c
respectively

3.0 Results
The data provided in the following figures was extracted from a
SPIC