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Enter Product Name In Document Properties Panel June 21, 2004
Product Specification
June 21, 2004
1
ATM Adaptation Layer 5 (AAL5)
4.0
Modelware
10 West Bergen Place, Suite 105
Red Bank, NJ 07701
USA
Phone: +1 732 936 1808
Fax: +1 732 936 1838
E-mail: info@modelware.com
URL: www.modelware.com
Features
Available under terms of the SignOnce IP
License
Compliant to ITU-T I.363.5 specification
Scalable design up to 32K connections.
Packet size up to 32K bytes.
CPCS Trailer generation and checking, including CRC-32.
Reassembly timers to detect lost cells.
AAL0 mode support.
User-programmable loss priority and congestion indication per message.
User-programmable UU octet per message.
User-programmable VPI/VCI per virtual connection.
Operation administration and maintenance OA&M cell insertion and extraction.
Up to 5Gb duplex data processing capacity.
Includes UTOPIA Master/Slave Level 1/2/3 as a part of the core.
AllianceCORE Facts
Provided with Core
Documentation
User Guide, Design Guide
Design File Formats
EDIF netlist, Verilog, VHDL
Constraints Files
AAL5_Top_<device name>.ucf
Verification
Test Bench, Test Vectors
Instantiation templates
VHDL, Verilog
Reference designs &
application notes
Application Guide
Additional Items
None
Simulation Tool Used
ModelTechs Modelsim
Support
Support provided by Modelware., Inc
Table 1: Example Implementation Statistics
Family
Example Device
Fmax
(MHz)
Slices
1
IOB
2
GCLK BRAM MULT
DCM/
DLL
MGT
PPC
Design
Tools
Spartan-3
XC3S2000-4
71
2380
3
407
2
21
0
0
N/A
N/A
ISE 6.1.03i
Virtex-II Pro XC2VP7-6
100
3044
3
417
2
29
0
0
0
0
ISE 6.1.03i
Virtex-II
XC2V2000-6
100
2809
3
414
2
24
0
0
N/A
N/A
ISE 6.1.03i
Notes:
1) Actual slice count dependent on percentage of unrelated logic see Mapping Report File for details
2) Assuming all core I/Os and clocks are routed off-chip
3) VirtexIIPro (256 channel design), VirtexII (128 Channel design) and Spartan-3 (32 channel design) are example sizes. ATM Adaption Layer 5 (AAL5)
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June 18, 2004
Figure 1: AAL5 Foundation Block Diagram
Features (continued)
Fully automatic test bench including sophisticated.
User interface is extendable to support variety of interfaces.
Optional integration with Modelwares Gigabit/100/10 Ethernet, Frame Relay, AAL 1, and AAL 2 cores.
Configurable VCI/VPI to VCID decoding using one of the following techiniques:
External/Internal CAM for full/partial VCI/VPI Range Lookup
Programable VCI/VPI bit decoding
Applications
The AAL 5 Foundation core is used for applications that allow errored packet delivery. In this mode, user
packets (CPCS-SDUs) are received in 48-byte segments (CPCS-IDUs), except for the last segment,
which may be smaller than 48-bytes. Cell payloads received from the ATM side are also passed through
to the user as they arrive. Since the core does not buffer complete packets, the memory usage is small.
A typical application is shown in the Figure 2 below.
UTOPIA
Level 1/2/3
Cell
FIFO
&
Rate
Adaptation
Reassembly
Controller
PluriBus
Output
Interface
Segmentation
Controller
PluriBus
Input
Interface
UTOPIA
Level 1/2/3
Cell
FIFO
&
Rate
Adaptation
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control
Data
Control Modelware Inc.
June 21, 2004
3
AAL5 Foundation
User Logic
ATM Layer
AAL5
Foundation
Segmentation
AAL5
Foundation
Reassembly
CAM
(Optional Reverse
VCID Lookup)
PluriBus
Interface
Cell Interface
(Utopia 1/2/3)
Figure 2: AAL5 core application
The AAL5 Foundation Segmentation block attaches the ATM header for every cell of the segmented
packet, and calculates and appends the padding, length and the CRC-32 fields. Complete cells are
stored in a FIFO for delivery to the ATM Layer over the UTOPIA interface.
The AAL5 Foundation Reassembly block decodes the ATM header for every cell and checks the running
CRC and length on the last cell. The ATM cell payload excluding the pad is forwarded to the packet
interface.
General Description
Modelware offers two modular products for AAL 5: Foundation and Manager. The AAL 5 Foundation
core implements the Common Part of the AAL type 5, including the CPCS and the SAR in Streaming
Mode. In addition, the AAL 5 Foundation core performs ATM header insertion and extraction, which are
ATM Layer functions. The AAL 5 Manager core includes the Foundation core and the memory
management functions needed to support the AAL 5 Message Mode.
On the Service Access Point (SAP) side, both AAL 5 cores interface to the users circuitry through an
easy to use packet interface. On the ATM side, the cores interface to an ATM switch through a UTOPIA
interface
Functional Description
Segmentation Section
The Segmentation Section block diagram is shown in Figure 2. The Modelware AAL5 Foundation
segmentation engine receives complete packets or bursts that are either multiple of 48 bytes or contain
an EOP (end-of-packet). Each packet or burst is associated with a VCID (or VPI/VCI). The packets or
bursts are converted into ATM cells with the appropriate header with VPI/VCI fields that are read from the
Connection Table or received directly from the user interface. For each cell that is processed, the core ATM Adaption Layer 5 (AAL5)
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June 18, 2004
stores intermediate length and CRC values. The last cell (or both last and before last) is appended with
the appropriate pad bytes and the AAL5 trailer including the length and CRC fields.
Segmentation
Controller
Connection
Table
(Optional External
Memory Usage)
Input
Interface
Segmentation
State
Memory
S_Valid
S_Data
S_Valid
S_CLP
S_Avail
S_CI
S_VCID
S_SOP
UTOPIA
(Level 1/2/3)
Cell
FIFO
&
Rate
Adaptation
S_Reset_n
S_Clk
S_EOP
S_Mod
S_UU
S_Abort
Rd
M
a
pD
at
R
d
M
a
pA
dd
r
Temporary
Storage
Memory
S_VCI_VPI
Data
Control
Data
Control
ATM
Cell
Burst /
Packets
Data
Control
Data
Control
Required Block/Signal
Optional Block/Signal
Internal Memory Only
Internal/External
Memory Usage
S_MapWr_n
S_MapVCID
S_MapATMChan
Cell
Storage
Memory
S_OEM_WrEnb_n
S_OEM_SOPC
S_OEM_Data
S_CPI
S_MapVCI
S_MapVPI
S_OEM_Chan
Figure 3: Segmentation Section Block Diagram Modelware Inc.
June 21, 2004
5
Reassembly Section
The Reassembly Section block diagram is shown in Figure 4.
The Modelware AAL5 Foundation reassembly engine receives multiplexed ATM cells from different
connections. Using the direct VCI to VCID mapping or VCI/VPI to VCID mapping using an external
Content Addressable Memory (CAM), the VCID corresponding to each ATM cell is obtained. As each
ATM cell is received for each connection, intermediate length and CRC values are calculated and stored.
The ATM cell payload is forwarded to the user along with the VCID. When the last cell is received, the
length and CRC values are checked and reported to the user using the receive status signals. Timers
are used detect dead connections. If a timeout occurs, the connection is closed with and an error is
reported using the receive status signal available on the Output Interface.
UTOPIA
Level 1/2/3
Cell
FIFO
&
Rate
Adaptation
Reassembly
Controller
Output
Interface
Reassembly
State
Memory
Reset_n
R_Clk
R_Avail
Reassembly
Timers Process
Memory
ATM
Cell
Burst /
Packets
Data
Control
CAM
(Optional for reverse VPI/
VCI to VCID Lookup)
RdMapDat
RdMapAddr
R_MapWr_n
R_MapAddr
R_MapData
Data
Control
Data
Control
Data
Control
Last Cell Storage
Memory
Cell Storage
Memory
R_OEM_WrEnb_n
R_OEM_SOC
R_OEM_Data
Required Block/Signal
Optional Block/Signal
Internal Memory Only
Internal/External
Memory Usage
R_OEM_Chan
R_Valid
R_Data
R_CLP
R_CI
R_VCID
R_SOP
R_EOP
R_Mod
R_UU
R_RS
R_PktLenght
R_CPI
R_BurstSize
Figure 4: Reassembly Section Block Diagram
Core Modifications
The AAL5 core can be easily configured using parameters to meet the requirements of a particular
application. Furthermore, parameters enable the synthesis tool to remove logic that is not required for
the selected configuration, resulting in a more efficient implementation.
The parameters used in the core are defined in Table 2. ATM Adaption Layer 5 (AAL5)
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June 18, 2004
Segmentation Parameters
Parameter
Type
Range
Description
ActiveSegVCIDs
Integer
1 - 65536
Active Number of Connections on
Segmentation Side: Sets the number of active
connections supported by the core.
Note: The number of active connections is
generally a smaller than the maximum number of
connections supported by the system. It
represents the number of channels undergoing
packet segmentation simultaneously. Refer to
Appendix A for more details on active connections.
SegFifoAddrBits
Integer
> 4
Segmentation FIFO Address Bits: The Number
of address bits to specify the Segmentation FIFO
size. The recommended minimum is 5 to be able
to store at least 2 48-byte bursts.
CPCS_IDU_Length
Integer
12 16
CPCS IDU Length in words: The cell payload
size in 32 bit words.
For standard 48 bytes payload in an ATM cell, this
value must be set to 12.
UTMChan
Integer
> 0
UTOPIA Number of channels: Sets the number
of channels for multi-phy utopia.
UTMTxDBits
Integer
8, 16, 32
UTOPIA Data Width: Sets the data widt