110 Fulbourn Rd. 14911 Quorum Drive,
Cambridge, UK Dallas, Texas, USA

David.Howard@arm.com

Kaijian.Shi@synopsys.com




A
BSTRACT

Various current control techniques are described to limit current
surge when sleep transistor are turned on to power a design.
Advantages and disadvantages in the techniques are also discussed.
The trade-off consideration on power-on latency adds more
challenges in the current control in sleep transistor implementations
which are addressed in the paper.
I
NTRODUCTION

Power-gating is the most effective standby-leakage reduction
method recently developed [1]-[6] for sub-130nm low-power
applications such as hand-held devices and battery operated
equipments. In a power gating design, sleep transistors are used as
switches to shut off power supplies to parts of a design in standby
mode. A sleep transistor is either a PMOS or NMOS high Vth
transistor that connects permanent power supply to circuit power
supply which is commonly called virtual power supply. The sleep
transistor is controlled by a power management unit to switch on and
off the power supply to the circuit. Besides the challenges in the
sleep transistor design optimization that we have addressed in a
separate paper, critical issues such as power-on current surge in the
sleep transistor implementations must be addressed to ensure the
power-gating design works correctly when the sleep transistors are
switched on. In a power-gating design, hundreds of sleep transistors
are implemented to provide sufficient drive current to the design.
When the design is coming out of the sleep mode, the sleep
transistors are switched on to supply power to the design. The
simultaneous switching current for charging the design to a full
power-on state can reach tens of Amps. Such large current surge will
cause large IR-drop in the design because of the limited power
supply in the battery operated devices. The large IR-drop will in turn
cause malfunctions in the design due to IR-drop induced
performance degradation and noise bumps. In the worst case, the
large current surge could result in short term VDD collapse causing
the state saved in retention registers and memories to be corrupted.
Therefore, it is critical to have power-on current control techniques
in the sleep transistor implementations to limit the current surge.
Both resistive effects (IR-drop) and the inductive effects caused by
the step change in current (large dI/dt) need to be considered. In this
paper, we analyze various power-on current surge situations, explain
the causes and describe corresponding techniques to control the
power-on current in the sleep transistor implementations.
R
OW BY ROW POWER
-
UP METHOD

One possible solution is to separate the chip power supply net into
individual rows, each powered up by one or a few sleep transistors.
At power-up the controller would then turn on the sleep transistors in
each row in sequence. This limits power-on current to the charge of
one row. However, there are two major issues in the method. Firstly,
there is the potential for large crowbar currents caused by
connections between cells in powered-on row and other rows and
secondly there are timing issues brought about by local variations in
power supply voltage.
The crowbar currents may come about the two ways :
- Large current in a powered-on row caused by floating inputs
driven by other un-powered rows. This may cause long power-up
time in weak switch charging or current surge in strong switch
charging period.
- Large current in cells in already powered-on rows driven by
very slow ramp-up cells in the power-on row.
Both these could cause a current surge in VDD and possible IR-
drop large enough to corrupt logic states in neighborhood active
blocks.
Separated power supplies for each row will introduce local
dynamic IR-drop which in turn will lead to delay variations. This
may cause chip malfunction because of hold time violations.
Although this can be addressed by conservative design parameters,
applying large hold margin to the design to cover the variation is
costly in chip areas - experiment shows that 0.1ns more hold margin
in 90nm design could result in 20% chip area increase due to buffer
insertion.
This strategy is unlikely to become common-place unless a robust
solution to these two problems can be found.
C
HAINED POWER
-
UP METHOD

Another solution is to turn on the sleep transistors consecutively,
i.e. in a daisy chain style. In this case, the power-on current increases
with the number of turn-on sleep transistors.
However, the current surge resulting from this method could still
be too large unless the daisy-chain is very slow. The delay through a
typical chain of inverters, for example, is likely to be much shorter
than the time required to power up a large macrocell or voltage
island, so it is likely that the peak value of the current will be large,
and it will be directly proportional to the number of header switches
in the macrocell. A larger propagation delay could be introduced
using on-chip resistive elements such as a long polysilicon resistor,
but slowly rising voltages on circuit inputs could introduce other
problems such as crow-bar currents and hot electron effects.
The graph shows the current profile in a simple 6-row test circuit.
A typical macrocell is more likely to have 300-600 rows, so the
current peak for a large design is likely to be in excess of 1A. FIGURE 1. VDD current when sleep transistors are tuned on.

T
WO STAGE POWER
-
ON METHOD

Another approach is to split the switch transistors into two arrays:
a weak transistor array and main transistor array. At power on, the
weak transistors are turned on to trickle charge the design. The
limited current-flow of the weak sleep transistors constrains the
power-on current rush. When the design is charged to a voltage close
to VDD, the main header transistor array is turned on ready for
normal operation. One possible control mechanism for the turn-on
sequence of both arrays is a daisy chain of buffers, as shown in the
diagram opposite, which once again spreads out the turn-on time and
reduces dI/dt.

FIGURE 2.Two stage power-on daisy chains.
The size of the weak trickle transistors is determined by the
desired maximum current limit of the design although it may also
need to consider the maximum permissible turn-on delay time. A
smaller trickle current may reduce the total surge current, but also
increases the time taken to bring the system out of sleep mode.
The following two graphs show clearly the effect of different
transistor sizes used for the weak trickle charge for the 6-row test-
case. The smallest transistors have the lowest current peak, but take
much longer for the switched power supply to reach 90% or even
80% of the final operating voltage. The designer must decide how
much current flow is acceptable, based really on how much voltage
perturbation is acceptable at the storage elements. Another
consideration is how those weak header transistors are distributed
across the cell - they may be cluster together in a single region or
column for easy control, or they may be scattered across the whole
layout to minimize local IR drop.
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
0.00
100.00
200.00
time /nsec
s
w
i
t
ch
ed
su
p
p
l
y
vo
l
t
ag
e
/v
W=0.8um
W=1.2um
W=1.6um
W=2.0um

FIGURE 3. Power-on voltage curve

-8.00
-7.00
-6.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
0
50
100
150
200
250
time /nsec
V
DD cu
r
r
en
t
/
m
A
W=0.8um
W=1.2um
W=1.6um
W=2.0um

FIGURE 4. Power-on current curve
T
RICKLE CHARGE END CONTROL

Once the weak transistor array configuration has been
determined, a decision must be taken about when to turn on the Main
Header array. To avoid a potentially hazardous current spike, this
should be delayed as long as possible, but this adds to the response
time of the system, which may also be an important design
parameter.
The graph below shows the time taken for the switched VDD to
reach different voltage thresholds (expressed as percentages of VDD
voltage) with the four different weak header transistor sizes.
Time to reach Main Header Threshold
0.00ns
20.00ns
40.00ns
60.00ns
80.00ns
100.00ns
120.00ns
140.00ns
160.00ns
180.00ns
75%
80%
85%
90%
95%
100%
Main Header enable threshold as percentage of VDD
c
h
a
r
gi
ng t
i
m
e

W=0.80um
W=1.2um
W=1.6um
W=2.0um

FIGURE 5. Time to reach main header threshold.
w

w

w

w

Controller

Weak trickle transistors

Main Header switches

Switched
supply
To logic gates
VDD current when Header sw itch is turned on
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
10.00
0.00
10.00
20.00
30.00
time /nsec
cu
rren
t
/
m
A
VDD
current Once the Main Header is enabled, a much larger current starts to
flow into the switched power supply. The profile of this current is
strongly dependent on how the Main Header transistors themselves
are controlled, and also how they are distributed, since the resistance