. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Why Include Spare Cells in an ASIC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Spare Gate Cells in the Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Using the Synplify ASIC Tool to Preserve Spare Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Set-up Spare Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Design Flow Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Optimize Instantiated Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Synplify ASIC Support for Spare Gates
Overview
Page 2
Synplicity, Inc. Application Note
Overview
It is possible for an ASIC design team to yield first silicon that contains minor logic
errors. Whenever possible, it is preferable to fix those errors by making only minor
changes to a metal-layer mask. If the spare gates that were included in the design and
existing logic gates can be reconnected to fix the logic error, the schedule impact and
cost can be kept to a minimum.
This document describes how to preserve spare-gates in an ASIC design using the
Synplify ASIC
®
tool. The document also explores some of the methodologies that
various designers use to implement spare gates in ASIC designs.
Why Include Spare Cells in an ASIC Design
When silicon comes back and a design problem is uncovered, an engineering change
order (ECO) is required. If the fix must be made to the base poly-silicon layer, modifi-
cations to the remaining masks are required to accommodate the change. If the
change can be accomplished by modifying only one or two metal-layer masks as
opposed to changing the base layer, the costs and time impact are dramatically
reduced.
To support modifying the metal-layer mask, many design teams include spare cells in
the design to provide a level of insurance against re-spin costs for minor design ECOs.
In this way, the design changes (hopefully not major, structural problems) can be
accomplished using the spare gates and relatively minor changes to one or more of the
metal layers.
In some situations a focused ion beam process is used to drill down and then diffuse a
wire to accomplish this kind of metal-only circuit change. However, the changes are
usually made to one or more of the metal-layer masks, then a new wafer/die set is
manufactured for which the base silicon is unchanged.
To provide a netlist containing spare gates requires that logic gates included as spares
are not optimized away by synthesis or other design tools in the ASIC design flow.
Additionally, the connectivity and placement of the gates should be controlled to allow
use for possible circuit fixes.
Spare gates are most useful when they are physically near the location of the flawed
logic. Therefore, spare gates need to be arranged across the chip rather than gathered
in one tight location. Example Design
Synplify ASIC Support for Spare Gates
Synplicity, Inc. Application Note
Page 3
Example Design
Example designs are provided in both VHDL and Verilog and can be used to demo or
explore. The example is an eight-bit micro controller design with two blocks
containing spare cells. The design file directory includes a demo and golden directory
and a c_shell script to clean the demo directory. Projects are complete and the
directory structure is setup relative to the project. You should be able to install and run
the design from any location without requiring adjustments to the path.
You can open the project file from the Synplify ASIC UI:

For Verilog,
8bit_ver.prj
For VHDL,
8bit_vhd.prj
Synplify ASIC Support for Spare Gates
Example Design
Page 4
Synplicity, Inc. Application Note
Spare Gate Cells in the Example
The example design uses two sets of spare gates: SPARE1 and SPARE2, as shown in the
following figure.
Figure 1: RTL View of Two Spare Gate Blocks Example Design
Synplify ASIC Support for Spare Gates
Synplicity, Inc. Application Note
Page 5
Each spare block contains an XOR cell and instantiated register, as shown in the
following figure.
Figure 2: RTL ViewInterior of Spare Block
Cell
spare_dff
is the instantiated AMI cell,
df001
.
Figure 3: RTL View of spare_dff Synplify ASIC Support for Spare Gates
Example Design
Page 6
Synplicity, Inc. Application Note
The next figure shows a hierarchical representation of the spare cells in the final
implementation (Technology view).
Figure 4: Hierarchical View in the Final Implementation
There are two spare-gates blocks each showing instantiated AMI cells
df001
and
eo21

with inputs set to zero and unconnected outputs. Using the Synplify ASIC Tool to Preserve Spare Gates
Synplify ASIC Support for Spare Gates
Synplicity, Inc. Application Note
Page 7
Using the Synplify ASIC Tool to Preserve Spare Gates
Synplify ASIC releases 3.0.3 and later support spare gates. Earlier releases supported
spare gates using a combination of: syn_hier= hard
syn_noprune
syn_preserve
syn_keep
syn_no_reopt

No change in earlier HDL containing spare gate logic is required to use the later
releases, however, with Synplify ASIC version 3.0.3 and higher, you can use the
following procedure to more easily preserve the intended gates.
Set-up Spare Gates
1. Instantiate the spare gates within a separate block or blocks in the design.
2. Apply syn_hier = fixed to the blocks containing spare gates (the immediate parent for
the spare gates).
3. Apply syn_no_reopt = 1 to the blocks containing spare gates (the immediate parent for
the spare gates).
Define these attributes, in the
.sdc
file, to the block/entity/module (called a view
object) using
v:
prefix before the object name
.
For example:
v: object_name syn_hier {value}
Following is an example showing these attribute definitions using the SCOPE
®
UI:
Figure 5: SCOPE UI Constraint Definition Synplify ASIC Support for Spare Gates
Using the Synplify ASIC Tool to Preserve Spare Gates
Page 8
Synplicity, Inc. Application Note
Following is an example showing these attribute definitions in the Tcl-format
.sdc

constraint file:
# Attributes
define_attribute
{v:work.spare_dff_v} syn_hier {fixed}
define_attribute
{v:work.spare_dff_v} syn_no_reopt {1}
define_attribute
{v:work.spare_xor_v} syn_hier {fixed}
define_attribute
{v:work.spare_xor_v} syn_no_reopt {1}
#
Notes A hierarchical block with spare gates can contain only spare gates and cannot be ran-
domly mixed with RTL or non-spare gates. The
syn_hier
and
syn_no_reopt
attributes are applied to the hierarchical block (applied to
the immediate parent of the instantiated spare gate).

syn_hier=fixed
makes sure constants (and/or inversions) are not pushed across the
block boundary and ensures the port list of the block is not optimized or otherwise
changed. syn_no_reopt 1
makes sure instantiated cells to which this attribute is applied are not
resized or otherwise optimized.
syn_no_reopt
can be applied to a block (view
v:
),
which applies the attribute to the instantiated cells in that block. Please see
Appen-
dix on page 10
for more details on these attributes. Spare gates/cells should be instantiated and grouped in separate hierarchical block(s).
The spare-cell blocks may be broken down to multiple blocks that each relate to a cer-
tain set of logic so that the spare gates can be physically placed near that logic on the
chip. This eases the back-end flow and ensures that the gates are distributed/placed
according to how they might be needed, reducing the difficulty of the metal-mask-only
ECOs. If all spare gates are defined in one block, they might be physically placed that
way. Be sure you work directly with the P&R team to locate the spare gates as required.
Some back-end tools have the ability to spread the cells out automatically. For example,
Cadences First Encounter terms this spare cell shot-gunning. There is no limit to the number of spare-gate blocks within the design. This allows the
designer flexibility needed to break up the spare gates so that they can be more easily
scattered about the ASIC, or so that they can be located near specific logic that is sus-
pected of a higher probability of requiring an ECO. Each spare gate must be instantiated. There is no support currently for spare gates/
cells described by behavioral RTL. Spare gates/cells must be instantiated. The spare gates inputs can be connected to logic level high or low. To prevent the gate
from oscillating (creating noise and consuming power), the inputs are usually tied to
ground or power as appropriate. The inpu