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AN221K04 Development Board User Manual AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 1 of 17
1.0 Overview
The Anadigmvortex development board is an easy-to-use platform designed to help you get started with
implementing and testing your analog designs on the Anadigmvortex FPAA silicon devices.
While the device on this development platform is an AN221E04 device, you can use this board to implement all
of your AN221E02, AN120E04, AN121E04, AN220E04 and AN221E04 designs. The design software -
AnadigmDesigner
�
2 can use the AN221E04 device on board to implement designs done using any device in
the Anadigmvortex device family.
This manual provides an overview on how to effectively use this board to implement your analog design. But
first, here are some salient features of the Anadigmvortex development board:

Small footprint 4 by 4 inches

Large breadboard area around the AN221E04 device

Header pins for all the FPAA device analog I/Os

Ability to separate, electrically and physically, the digital section leaving a purely analog board with SPI EPROM and digital
interface pins

Four (jumper configurable) analog interface blocks for level-shifting, amplifying, attenuating, filtering and differential to single-
ended conversion of the signal

A spare opamp powered to 5V that can be used to buffer the +0.5V or +3.5V references or an analog signal

Daisy chain capability that allows multiple boards to be connected to evaluate multi-chip systems

Standard PC serial interface for downloading AnadigmDesigner
�
2 circuit files

On-board 16-MHz oscillator module
Figure 1: The NEW Anadigmvortex Development Board AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 2 of 17
2.0 Layout
Figures 2 and 3 show the layout of the board allowing easy location of all the components, power connections
and jumpers.
scale in cm
Se
r
i
a
l
Po
r
t
S
o
cke
t
Analog Digital
FPAA
bread
board
bread
board
Power
bread
board
analog I/Os
analog I
/
O
s
VMR
VM
R
daisy
daisy
SPI
EPROM
dual
opamp
(skt)
Anadigm logo
Analog
Interface
Block #4
Analog
Interface
Block #3
Analog
Interface
Block #2
Analog
Interface
Block #1
spare
oamp pins
RST
button
S
e
ri
al
N
u
mber
EXECUTE
PORb
ACTIVATE
ERRb
DIN
DCLK
CS2b
SARCLK
SARDATA
SARSYNC
LCCb
GND
+5V
po
w
e
r
pow
er
power
power
vref
AN221D04-DEV
v2.02
16MHz
Clock
D
i
g
i
ta
l Se
c
t
io
n
power
Figure 2: Top-level layout of the Anadigmvortex development board AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 3 of 17

power screw
terminal
power jack
socket
dual opamps
(socketed)
reset
button
16MHz
osc module
daisy
input
digital signal
pull-ups/downs
jumpers
serial
port
socket
power for
breadboard
(0V, +2V, +5V, V+, V-)
daisy
output
analog I/O
& buff VMR
header pins
FPAA
EPROM
(socketed)
dual opamp
(socketed)
digital i/f
jumpers
PIC program
header
PIC
PIC
ADC i/ps
daisy
config jumpers
logo &
board name
space for
serial number
#1 of 4 footprints
for SMA or BNC
socket
#1 of 4
test points
18.432MHz
crystal
power & ground
split between
digital & analog
red & green
LEDs for config
pass/fail
green LED
for power on
#1 of 4 jumper
blocks to config
analog i/f blocks
#1 of 4 blocks of
discrete Rs & Cs
to config analog i/f
blocks
VREF pins
(0.5, 3.5, 2V)
spare
opamp
pins
Figure 3: Detailed layout the Anadigmvortex development board
3.0
Powering up the Anadigmvortex Development Board
The options for powering up the board are as follows:
Connect wire from a dual precision, regulated supply to the on-board 3-way terminal with negative
post at 0V to -10V, middle post at ground, positive post at +5.5V to +10V, OR
Connect wire from a single precision, regulated supply to the on-board 3-way terminal with negative
post shorted to middle post, +5.5V to +10V across middle and positive posts (cannot use ground
referenced signals with analog interface blocks with this mode because V- = 0V), OR
Use an AC wall converter (regulated)and connect into the supply jack socket, 10.5V minimum, 20V
maximum
WARNING
When using an AC wall converter or brick it is important to note the following:
1.
The output must be between 10.5V and 20V. A 9V power unit will not work.
2.
The output must be regulated if it is intended to use the analog interface blocks.
3.
Do not connect the ground post to the negative post of the 3 way screw terminal. This will blow
one of the regulators.
4.
Be aware that some of the components in the power circuit get hot.
5.
When daisy chaining boards, use a single AC converter into one of the boards and common
together the negative, ground and positive posts of the screw terminals of all the boards. AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 4 of 17
3 way
screw
terminal
jack
socket
analog
interface
blocks
x4
+5V
GND
FPAA
digital
circuit
V+
V-
+5V
reg
250mA
20R
2W
+5V
reg
470R
vmr
buff
eprom
Figure 4: Power Circuit
There is a green LED to indicate that the board is successfully powered up. The current through the FPAA,
VMR buffer, EPROM (if used), digital circuitry and anything else connected to the +5V supply on the board is
limited to 250mA when using the jack socket power input.
Note: the positive and negative supplies (V+ and V-) determine the amplitude range of signals used with the
analog interface blocks.
4.0
Analog Interface Blocks
There are four (4) identical analog interface blocks (figure 5), each with 4 jumpers, a low noise opamp

and a set
of through-hole resistors and capacitors. These 4 blocks are each connected to an analog input/output pin of
the AN221E04 FPAA device. This allows all 4 blocks to be used as either an input or output interface. The 4
blocks are laid out in order up the left side of the board with block #1 at the bottom and block #4 at the top.
Each block has a footprint that will take a variety of sockets including SMA and BNC. There is also a test point
(TP1-4) and ground point in which the user can solder loops of wire for the connection of probes.
_
+
+V
-V
R1=100k 1%
R2=100k 1%
C1=1.8p
R3=100k 1%
R4=100k 1%
C2=1.8p
VMR
GND
GND
IxN
SKT
IxP
IxP
SKT
J1
J2
J3
J4
Figure 5: Analog Interface Block (#1 of 4)
If the 4 jumpers are in the upper position then the block is configured as an input stage, level shifting the ground
referenced single-ended input to +2V (figure 6).

The negative differential input of the FPAA has been shorted to
buffered VMR by placing a jumper between its header pin and VMR. The gain of this circuit can be changed by
changing the values of the resistors. The gain is given by the following equation:
Gain = R2 / R1 = R4 / R3
- R3 = R1 and R4 = R2 AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 5 of 17
FPAA
R1=100k
+2V ref
Single-Ended
Signal
GND ref
Single-Ended
Signal
_
+
+V
-V
I1P
R3=100k
R2=100k
R4=100k
GND
VMRC
+2V
buffer
I1N
socket
SB1
C1=1.8p
C2=1.8p
jumper
positions
J1 J2 J3 J4
header
pins
Figure 6: Input Level-Shifter (block #1)
If the jumpers are in the lower position then the block is configured as an output stage (figure 7). This figure
shows an analog interface block configured as an output, level shifting the +2V referenced differential output
from the FPAA to ground and converting it to single-ended. The gain of this circuit can be changed by changing
the values of the resistors. The gain is given by the following equation:
Gain = R2 / R1 = R4 / R3
- R3 = R1 and R4 = R2
Note: The output signal from the circuit cannot exceed the supply voltages to the opamp (V+ and V-). Also the 2
input resistors should not be significantly lower than 100k so as to not overload the FPAA outputs.
FPAA
GND ref
Single-Ended
Signal
+2V ref
Differential
Signal
I1P
I1N
GND
socket SB1
or
test point TP1
R1=100k
_
+
+V
-V
R3=100k
R2=100k
R4=100k
C1=1.8p
C2=1.8p
(configured
as outputs)
jumper
positions
J1 J2 J3 J4
Figure 7: Output Level-Shifter and Diff2Single Converter (block #1)
The analog interface block in figure 5 can also act as a low pass filter with the corner frequency adjusted by
changing the values of the 2 capacitors in figure 5. The default values for the capacitors is 1.8pF and this gives
a cut-off frequency at about 1MHz the response of the default circuit is shown in figure 8. To lower the cut-off
frequency you can replace these capacitors with larger ones, the value given by the formula below:
C = 1 / ( 2 * * R * Fc )
- Fc is the required cut-off frequency
- C refers to both capacitors (C1 and C2 in block #1)
- R refers to both feedback resistors (R2 and R4 in block #1) AN221K04 Anadigmvortex
Development Board User Manual
UM030900-U010e
Page 6 of 17
0
0.2
0.4
0.6
0.8
1
1.2
1
10
100
1000
10000
Frequency (kHz)
Ga
i
n
Figure 8: Frequency Response of Analog Interface Block with Default Components
Note: removing the capacitors altogether will not significantly increase the cut-off frequency and will also have
the effec