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A_New_Integrated_Circuit_for_Current_Mode_Control I
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APPLICATION NOTE
A NEW INTEGRATED CIRCUIT FOR
CURRENT MODE CONTROL
Abstract
The inherent advantages of current-mode control over conventional PWM approaches to switching power
converters read like a wish list from a frustrated power supply design engineer. Features such as automatic feed
forward, automatic symmetry correction, inherent current limiting, simple loop compensation, enhanced load
response, and the capability for parallel operation all are characteristics of current-mode conversion. This paper
introduces the first control integrated circuit specifically designed for this topology, defines its operation and
describes practical examples illustrating its use and benefits.
1.0
Introduction
Over the past several years an increased interest in
current-mode control of switching inverters has
surfaced in the literature. Originally invented in the
late 1960s this scheme was not publicly reported
until 1977
(1)
and has seen rapid development by
many authors to date.
(2-6)
In short, current-mode
control uses an inner or secondary loop to directly
control peak inductor current with the error signal
rather than controlling duty ratio of the pulse width
modulator as in conventional converters. Practi-
cally, this means that instead of comparing the error
voltage to a voltage ramp, it is compared to an
analogue of the inductor current forcing the peak
current to follow the error voltage.
FIGURE 1. A FIXED FREQUENCY CURRENT-MODE CONTROLLED
REGULATOR.
Figure 1 illustrates a simplified block diagram of a
fixed frequency buck regulator employing current-
mode control. As shown, the error signal,
is
controlling peak switch current which, to a good
approximation, is proportional to average inductor
current. Since the average inductor current can
change only if the error signal changes, the inductor
may be replaced by a current source, and the order
of the system reduced by one. This results in a
number of performance advantages including
improved transient response, a simpler, more easily
designed control loop, and line regulation compara-
ble to conventional feed-forward schemes. Peak
current sensing will automatically provide flux
balancing thereby eliminating the need for complex
balance schemes in push-pull systems. Addition-
ally, by simply limiting the peak swing of the error
voltage
instantaneous peak current limiting is
accomplished. Lastly, by feeding identical power
stages with a common error signal, outputs may be
paralleled while maintaining equal current sharing.
Although the advantages of current-mode control
are abundant, wide acceptance of this technique
has been hampered by a lack of suitable integrated
circuits to perform the associated control functions.
This paper introduces a new integrated circuit
designed specifically for control of current-mode
converters. Circuit function and features are des-
cribed in detail, and a comparative design example
is used to illustrate the numerous advantages of this
approach.
UC1846 Chip Architecture
In addition to all the functions required of conven-
tional PWM controllers, a current-mode controller
3-1 APPLICATION NOTE
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FIGURE 2. UC1846 BLOCK DIAGRAM
must be able to sense switch or inductor current
and compare it on a pulse-by-pulse basis with the
output of the error amplifier. As may be seen in the
block diagram of Figure 2, this is accomplished in
the UC1846 by using a differential current sense
amplifier with a fixed gain of 3. The amplifier allows
sensing of low level voltages while maintaining high
noise immunity. A list of other features, while not
unique to current-mode conversion, demonstrates
the advanced, state-of-the-art architecture of the
UC1846:
A ± 1%, 5.1V trimmed bandgap reference used
both as an external voltage reference and inter-
nal regulated power source to drive low level
circuitry.
A fixed frequency sawtooth oscillator with varia-
ble deadtime control and external synchroniza-
tion capability. Circuitry features an all NPN
design capable of producing low distortion
waveforms well in excess of 1 MHz.
3.0
An error amplifier with common mode range from
ground to
Current limiting through clamping of the error
signal at a user-programmed level.
A shutdown function with built in 350mV thresh-
old. May be used in either a latching, or non-
latching mode. Also capable of initiating a
hiccup mode of operation.
3-2
Under-voltage lockout with hysteresis to guaran-
tee outputs will stay off until reference is in
regulation.
Double pulse suppression logic to eliminate the
possibility of consecutively pulsing either output.
Totem pole output stages capable of sinking or
sourcing 100mA continuous, 400mA peak
currents.
These various features, along with their interrela-
tionships and applications to switched-mode regu-
lators, will be further discussed in the following
sections.
UC1846 Functional Description
3.1 Current Sense Amplifier
The current sense amplifier may be used in a var-
iety of ways to sense peak switch current for com-
parison with an error voltage. Referring to Figure 2,
maximum swing on the inverting input of the PWM
comparator is limited to approximately 3.5V by the
internal regulated supply. Accordingly, for a fixed
gain of 3, maximum differential voltages must be
kept below 1.2V at the current sense inputs. Figure 3
depicts several methods of configuring sense
schemes. Direct resistive sensing is simplest, how-
ever, a lower peak voltage may be required to min-
imize power loss in the sense resistor. Transformer
coupling can provide isolation and increase effi- APPLICATION NOTE
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ciency at the cost of added complexity. Regardless
of scheme, the largest sense voltage consistent
with low power losses should be chosen for noise
immunity. Typically, this will range from several
hundred millivolts in some resistive sense circuits to
the maximum of 1.2V in transformer coupled
circuits.
A.) RESISTIVE SENSING WITH GROUND REFERENCE
OUTPUT
R
SENSE
B.) RESISTIVE SENSING ABOVE GROUND
CURRENT
XFORMER
C.) ISOLATED CURRENT SENSING
FIGURE 3. VARIOUS CURRENT SENSE SCHEMES
In addition, caution should be exercised when using
a configuration that senses switch current (Figure
3A) instead of inductor current (Figure 3B). As the
switch is turned on, a large instantaneous current
spike can be generated in the sense resistor as the
collector capacitance of the switch is discharged.
This spike will often be of sufficient magnitude and
duration to trip the current sense latch and result in
erratic operation of the PWM circuit, particularly at
lower duty cycles. A small RC filter (Figure 4) in
series with the input is generally all that is required
to reduce the spike to an acceptable level.
FIGURE 4. RC FILTER FOR REDUCING SWITCH TRANSIENTS
3.2 Oscillator
Although many data sheets tout 300 to 500kHz
operation, virtually all PWM control chips suffer from
both poor temperature characteristics and wave-
form distortions at these frequencies. Practical
usage is generally limited to the 100 to 200kHz
range. This is a direct consequence of having slow
(f
t
= 2MHz) PNP transistors in the oscillator signal
path. By implementing the oscillator using all NPN
transistors, the UC1846 achieves excellent temper-
ature stabillity and waveform clarity at frequencies
in excess of 1MHz.
OUTPUT DEADTIME
FIGURE 5. OSCILLATOR CIRCUIT
Referring to Figure 5, an external resistor
is used
to generate a constant current into a capacitor
to
3-3

APPLICATION NOTE
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produce a linear sawtooth waveform. Oscillator fre-
quency may be approximated by selecting
and
such that:
2.2


C
T
(1)
Where
can range from 1K to 500K and
is
above 100pF. For quick reference a plot of fre-
quency versus
and
is given in Figure 6.
FREQUENCY - KILOHERTZ
FIGURE 6. OSCILLATOR FREQUENCY AS A FUNCTION OF
AND
Again referring to Figure 5, the oscillator generates
an internal clock pulse used, among other things, to
blank both outputs and prevent simultaneous cross
conduction during switching transitions. This output
deadtime is controlled by the oscillator fall time.
Fall time, in turn, is controlled by C
T
according to the
formula:
For large values of
(2)
= 145
(3)
A plot of output deadtime versus CT for two values of
is given in Figure 7.
Although timing capacitors as small as 100pF can
be used successfully in low noise environments, it is
generally recommended that C
T
be kept above
1000pF to minimize noise effects on the oscillator
frequency (see Section 4.0).
Synchronization of one or more devices to either an
external time base or another UC1846 is accomp-
lished via the bi-directional SYNC pin. To synchron-
ize devices, first, C
T
must be grounded to disable the
internal oscillator on all slaved devices. Second, an
external synchronization pulse must be applied to
the SYNC terminal. This pulse can come directly
from the SYNC terminal of a master UC1846 or,
alternatively, from an external time base as shown
in Figure 8.
OUTPUT DEAD TIME,
- MICROSECONDS
FIGURE 7. OUTPUT DEADTIME AS A FUNCTION OF TIMING
CAPACITOR C
T
3-4
FIGURE 8. SYNCHRONIZING THE 1846 TO AN EXTERNAL
TIME BASE
3.3 Current Limit
One of the most attractive features of a current-
mode converter is its ability to limit peak switch
currents on a pulse-by-pulse basis by simply limit-
ing the error voltage to a maximum value. Referring
to Figure 9, peak current limiting in the UC1846 is
accomplished using a divider network,