1 Output Board Hardware
2.4.2 Motor Driver Hardware
2.5.0 Processor Board


3.0 Software
3.1.0 Introduction to this section
3.2.0 Sensor Board
3.2.1 Sensor Board Software
3.3.0 Output Board
3.3.1 Output Board Software
3.4.0 Processor Board
3.4.1 Processor Board Software Introduction
3.4.2 Neural Network Weight and Neuron List
3.4.3 Neural Network - Access of Neuron and Weight lists
3.4.4 Neural Network - Random Number Generation
3.4.5 Neural Network - Testing a Neural Network: A Simple
Multi-Layer Perceptron example 3
3.4.6 Neural Network - Testing a Neural Network: A Simple
Backpropagation training technique for a Multi-Layer
Perceptron example

4.0 Neural Networks
4.1.0 Introduction to this section
4.2.0 Introduction to Neural Networks
4.2.1 What a Neural Network is useful for
4.2.2 How Neural Networks work
4.3.0 Implementing Neural Networks
4.3.1 A Multi-Layer Perceptron Neural Network
4.3.2 Other Multi-Layer Perceptron Functions
4.3.3 Multi Layer-Perceptron Training with Backpropagation

5.0 Conclusion

6.0 Bibliography

7.0 Revision Log

8.0 Appendix A C Source Code

9.0 Appendix B VHDL

10.0 Appendix C Block Diagram

11.0 Appendix D Schematics 4




1.0 - Introduction

1.1 Introduction to the Project

1.1.0 Introduction

The field of artificial intelligence is rapidly expanding. How are new algorithms tested
while under development? Of course it is not practical to design a finished Platform/' >product
assuming that a new algorithm will work perfectly, as undoubtedly the algorithm will
have a massive failure. Therefore, some custom hardware is designed that will test the
algorithm, and allow the developer to tweak the algorithm. However, when a different
algorithm is being developed and needs testing, it will be likely require new custom
hardware to be created.

The Embedded Artificial Intelligence Development Platform overcomes these problems,
by creating one piece of hardware that can test many different artificial intelligence
algorithms. These algorithms could take many forms such as complex neural networks or
state machines.

By using embedded microcontrollers in the hardware design, it is easy to see which
algorithms can easily work in real-time on small hardware. This is essential, as it means
you can use this development platform for developing artificial intelligence that will
work in small robots or large robots.

The project does not solely consist of the hardware. A set of routines that form the
framework for the entire system easily allow you to access data such as sonar readings,
an on-board camera, and motor controllers.

As well as the interface software, routines that perform useful tasks are also part of this
platform. These routines include high performance persorandom number generators,
memory access, and routines for creating and using neural networks. A user interface is
provided that works over the serial port and can connect to any computer with a serial
port.
5
Processor Board
Sensor Board
Output Board
Motor Driver Board
CMUCam Module
StannBus Interface
Right Motor
Control Logic
High Side
Charge Pumps
MOSFETs
MOSFET
Drivers
Right
Motor
High Side
Charge Pumps
MOSFETs
MOSFET
Drivers
Left
Motor
PWM
Direction
Left Motor
Control Logic
PWM
Direction
Vacuum Fluorescent Display
(VFD)
VFD Interface
Address
Decode
Data
StannBus Interface
Address
Decode
Data
Data Command
Decode
Colour
Tracking
Colour
Camera
Colour Tracking
Control
Ultrasonic
Transducer
Transducer
Driver
Transducer
Controller
StannBus Interface
Address
Data
Ferromagnetic
Random
Access
Memory
(FRAM)
(Storage
Medium)
S
t
o
r
a
g
e

M
e
d
i
u
m

C
o
n
t
r
o
l
Neuron List
Weight List
Power On Self
Test (POST)
Weight List
Generator
Neuron List
Generator
Random
Number
Generator
Artificial Neural
Network
Device Under Test
(DUT)
System
Control
StannBus Master
Controller
Stepper
Motor
Stepper
Motor Driver
Rotational
Sensor
Rotational
Sensor Signal
Amplifier
StannBus interface
Colour object tracking
Artificial Neural Network testing
Ultrasonics
Major Systems
Control Block Diagram
Motor control

Note: For full size block diagram see Appendix C 6
2.0 Hardware

2.1 Power Distribution

2.1.0 Introduction

The power in this system is very important, like in any system. Batteries are used to
provide power at different voltages as required.

2.1.1 Battery Types

There are a few voltages required. They are
7-10 volts
Electronics (including ultrasonics), regulated down to
required logic voltages
6 volts
Stepper motor
3 4 volts
Driver motors

A NiCad battery pack at 9.6 volts with approximately 900mAh capacity is used to power
the electronics.

The 6 volt power for the stepper motor is provided by a NiMH battery pack.

A custom 3.6 volt NiCad battery pack is used for the driver motors.

2.2 Backplane

2.2.0 Introduction

Plug-in Slots
StannBus
Controller
(CPLD)
JTAG Port
for CPLD
ISP Port
for Plug-In
Boards
R
S
2
3
2

Ser
i
a
l

P
ort
s
7

The backplane is the communications layer for the robot. It has four slots, into which four
expansion cards can be placed. One of these cards must be the processor-board. In this
way, it differs from the conventional PC where the processor is on the main board.
However, this makes changing the processor very easy, as it simply requires the
replacement of a single small board, and it doesnt require changing any of the peripheral
devices. Another advantage is that it is possible to add more advanced features, such as a
coprocessor using a digital signal processor (DSP). This would allow extremely fast
floating point math, which may be needed for some algorithms.

The protocol used in the communications between boards is known as the StannBus.
STANN is an acronym for Self Training Artificial Neural Network, which is a new
neural network being developed that will be tested on this hardware.

2.2.1 StannBus Connector Pin-Out

A




B
C




D
6 5 4 3 2 1
E
d
g
e

o
f
B
a
c
k
p
l
a
n
e

c
i
r
c
u
i
t

b
o
a
r
d
Backplane
2 1
A




B
C




D


The StannBus features two connectors per card slot on the backplane. One of the
connectors is the data connection; the other is the power connection. Both 3.3 volts
and 5 volts are available from the power connector. The data connector is an AMP part
number 536501-1, and the power connector is an AMP part number 536600-1.

Note: The 8-pin power connector has a pinout the same as that of the 24 pin data
connector (three pins on the circuit board per 1 blade on the connection side). The upper
right-hand pins on the circuit board are 20.42 mm (804 mil) apart.


8
Data Connector
Pin
Location
Pin Name
Input/Ouput
Description
A1
A0
Bi-directional
B1
A1
Bi-directional
C1
A2
Bi-directional
D1
A3
Bi-directional
A2
A4
Bi-directional
--
--

Address information for the bus. This is
shared between all slots, so the associated
board MUST tri-state this when
WR_STAT is low.

Address 0x00 is a RESERVED address
and must not be used.
C2
D0
Bi-directional
C3
D1
Bi-directional
C4
D2
Bi-directional
C5
D3
Bi-directional
D2
D4
Bi-directional
D3
D5
Bi-directional
D4
D6
Bi-directional
D5
D7
Bi-directional
Databus for the bus. This is shared
between all slots, so the associated board
MUST tri-state this when WR_STAT is
low.

As well alternate functions when
PROGRAM is high:
D0 MOSI D1 MISO D2 - SCK
A3
WR_REQ
Input
Pull this line high when the slow wishes
to have that status to write to the
StannBus. WR_STAT is used to tell the
board when this write request has been
acknowledged.
A4
WR_STAT
Output
This line goes HIGH when the slot can
write to the StannBus, if the line goes
low the Databus, Addressbus and Clock
lines MUST be tri-stated
A6
/RESET
Output
Connects to the reset of the processor or
system. If the processor is an Atmel AVR
it must connect to the AVR processor as
it is used in system programming. As
well the databus and addressbus MUST
be tri-stated when this pin is active,
unless the program pin is high. In this
case the in-system programming is
enabled and the databus does not have to
be tri-stated. This pin is active low.
B6
PROGRAM
Output
This pin is used for in-system
programming. When this pin goes high
the following connections should be
made from the databus and the Atmel
AVRs pins
D0 MOSI ISP Pin
D1 MISO ISP Pin
D2 SCK ISP Pin
B3
CLK
Bi-directional Clock defines when new data is present 9
on the data lines. This is shared between
all slots, so the associated board MUST
tri-state this when WR_STAT is low.

B5
TX
Input
Used for directly linking slots or
connecting the serial ports on the
backplane to the board plugged into this
slot.
C6
RX
Output
Used for directly linking slots or
connecting the serial ports on the
backplane to the board plugged into