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Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters
Quantization Resolution and Limit Cycling in Digitally Controlled PWM
Converters
Angel V. Peterchev
Seth R. Sanders
Department of Electrical Engineering and Computer Science
University of California, Berkeley
Abstract This paper discusses the presence of steady-state limit cy-
cles in digitally controlled pulse-width modulation (PWM) converters, and
suggests conditions on the control law and the quantization resolution for
their elimination. It then introduces single-phase and multi-phase con-
trolled digital dither as a means of increasing the effective resolution of
digital PWM (DPWM) modules, allowing for the use of low resolution
DPWM units in high regulation accuracy applications. Bounds on the
number of bits of dither that can be used in a particular converter are
derived.
I. I
NTRODUCTION
IGITAL controllers for pulse-width modulation (PWM)
converters enjoy growing popularity due to their low
power, immunity to analog component variations, ability to
interface with digital systems and to implement sophisticated
control schemes, and potentially faster design process. Their
applications include microprocessor voltage regulation mod-
ules (VRMs), audio ampliers, portable electronic devices,
and others.
This paper discusses the presence of steady state oscillations
(limit cycles) in digitally controlled PWM converters, as well
as techniques for increasing the effective resolution of digi-
tal PWM (DPWM) modules. Section II gives an overview of
the structure of digital PWM controllers. Section III describes
limit cycles and presents conditions for their elimination. Sec-
tion IV introduces controlled digital dither as a technique that
effectively increases the resolution of the DPWM module, al-
lowing for the use of low resolution DPWM modules in ap-
plications requiring high regulation accuracy, such as VRMs
and audio ampliers. The ability to use low resolution DPWM
modules in these applications, without incurring limit cycles,
can result in substantial power and silicon area savings.
II. D
IGITAL
C
ONTROLLER
S
TRUCTURE
A block diagram of a digitally controlled PWM converter
is shown in Fig. 1. Controllers with similar structure have
been discussed in a number of publications (e.g. [1], [2], [3],
[4]). The controller consists of an Analog-to-Digital Converter
(ADC) which digitizes the regulated quantity (typically the
output voltage
Î
ÓÙØ
), a DPWM module, and a discrete-time
control law. A typical discrete-time PID control law has the
form
´
·
½µ
Ã
Ô
´
µ
·
Ã
´
µ
 
´
 
½µ
·
·Ã
´
µ
·
Ö
´
µ
(1)
L
DPWM
(DAC)
law
control
Vout
Dref
Dc
Dout
ADC
Digital Controller
output filter
Vin
Cout
Fig. 1. Block diagram of a digitally controlled PWM converter.
where
´
µ
is the duty cycle command at discrete time
,
´
µ
is the error signal
´
µ
Ö
´
µ
 
ÓÙØ
´
µ
and
´
µ
is the state of an integrator
´
µ
´
 
½µ
·
´
µ
Further,
Ã
Ô
is the proportional term constant,
Ã
is the deriva-
tive term constant, and
Ã
is the integral term constant. All
variables are normalized to the input voltage,
Î
Ò
;
Ö
´
µ
represents the reference voltage, and
ÓÙØ
´
µ
is the digital rep-
resentation of
Î
ÓÙØ
. Variable
Ö
is used as a feedforward
term in (1). Note that
Ö
by itself would give the correct
duty cycle command for steady state operation with constant
load, if there were no load-dependent voltage drop along the
power train and no other non-idealities in the output stage [2].
III. L
IMIT
C
YCLES
For the converter of Fig. 1, limit cycles refer to steady-
state periodic oscillations of
Î
ÓÙØ
that are not due to the PWM
switching activity. Limit cycles may result from the presence
of signal amplitude quantizers like the ADC and DPWM mod-
ules in the feedback loop. Steady-state limit cycling is undesir-
able, since its amplitude and frequency are hard to predict, and,
consequently, it is difcult to analyze the resulting
Î
ÓÙØ
noise
and the electro-magnetic interference (EMI) produced by the
converter.
Let us consider a system with ADC resolution of
Æ
bits and DPWM resolution of
Æ
ÔÛ
Ñ
bits. For a buck con-
verter, this will correspond to voltage quantization of
¡Î
Î
Ò
¾
Æ
steps for the ADC, and
¡Î
ÔÛ
Ñ
Î
Ò
¾
Æ
ÔÛ Ñ
for Vout
Vref
time
voltage
1 bit error bin
0 bit error bin
-1 bit error bin
-2 bit error bin
transient
steady state
DAC levels
ADC levels
(a)
Vout
Vref
time
voltage
0 bit error bin
1 bit error bin
-1 bit error bin
-2 bit error bin
steady state
transient
DAC levels
ADC levels
(b)
Fig. 2. Qualitative behavior of
Î
ÓÙØ
for: (a) DPWM resolution lower than the
ADC resolution, and (b) DPWM resolution two times the ADC resolution
and with integral term used in the control law.
the DPWM. Fig. 2(a)
1
shows the behavior of
Î
ÓÙØ
in steady
state when the DPWM resolution is less than the ADC reso-
lution, and there is no DPWM level that maps into the ADC
bin corresponding to the reference voltage
Î
Ö
(this ADC bin
will be referred to as the zero-error bin). In steady state, the
controller will be attempting to drive
Î
ÓÙØ
to the zero-error bin,
however due to the lack of a DPWM level there, it will alter-
nate between the DPWM levels around the zero-error bin. This
results in non-equilibrium behavior, such as steady-state limit
cycling.
The rst step towards eliminating limit cycles is to ensure
that under all circumstances there is a DPWM level that maps
into the zero-error bin. This can be guaranteed if the resolution
of the DPWM module is ner than the resolution of the ADC.
A one-bit difference in the resolutions,
Æ
ÔÛ
Ñ
Æ
·
½
,
seems sufcient in most applications since it provides two
DPWM levels per one ADC level.
No Limit Cycle Condition # 1
Ö
×ÓÐ ÙØ
ÓÒ´
È
Ï
Å
µ
Ö
×ÓÐ ÙØ
ÓÒ´
µ
½
In all simulations the data is sampled at the switching frequency, therefore
the switching ripple on
Î
ÓÙØ
cannot be seen. For the discussions in this paper
the switching ripple is not of interest and its omission makes the plots clearer.
Yet, even if the above condition is met, limit cycling may
still occur if the feedforward term is not perfect and the control
law has no integral term (
Ã
¼
). In this case, the controller
relies on non-zero error signal
to drive
Î
ÓÙØ
towards the
zero-error bin. However, once
Î
ÓÙØ
is in the zero-error bin, the
error signal becomes zero, and
Î
ÓÙØ
droops back into the -1 bit
error bin. This sequence repeats over and over again, resulting
in steady-state limit cycling. This problem can be solved by
the inclusion of an integral term in the control law. After a
transient, the integrator will gradually converge to a value that
drives
Î
ÓÙØ
into the zero-error bin, where it will remain as long
as
¼
, since a digital integrator is perfect (Fig. 2(b)) .
No Limit Cycle Condition # 2
½
Ã
¼
An upper bound of unity is imposed on the integral term gain,
since the digital integrator is intended to ne-tune the output
voltage, therefore it has to be able to adjust the duty cycle com-
mand by steps as small as an
ÄË
.
The two conditions suggested above are not sufcient for
the elimination of steady-state limit cycles, since the non-
linearity of the quantizers in the feedback loop may still cause
limit cycling for high loop gains. Non-linear system analysis
tools, such as describing functions ([5], [6], [3]), can be used
to determine the maximum allowable loop gain not inducing
limit cycles. The feedback loop of the converter includes two
quantizersthe ADC and the DPWMhowever in the present
analysis we will consider only the ADC non-linearity, since it
performs coarser quantization if the DPWM resolution is made
higher than that of the ADC (as recommended above). The de-
scribing function of an ADC represents its effective gain as
a function of the input signal amplitude and DC bias. When
the control law contains an integral term, only limit cycles that
have zero DC component can be stable, since the integrator
drives the DC component of the error signal to the zero-error
bin. Thus the describing function of a round-off quantizer with
zero DC bias can be used to analyze the stability of the system.
This describing function,
Æ
´
µ
, is plotted in Fig. 3, where
is
the AC amplitude of the signal being quantized, and
¡Î
is
the quantization bin size corresponding to one
ÄË
. From the
plot it can be seen that the describing function has a maximum
value of about 1.3, corresponding to maximum effective ADC
gain. The control law can then be designed in the same way
as for linear systems, provided the effective gain of the ADC
is included in the loop gain calculations. Namely, to prevent
limit cycles it has to be ensured that
No Limit Cycle Condition # 3
½
·
Æ
´
µÄ´
µ
¼
holds for all non-zero nite signal amplitudes
and frequen-
cies
, where
Ä´
µ
is the loop transmission from the output
of the ADC to its input. 0
1
2
3
4
5
6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
A/ V
adc
[LSBs]
N(A)
Fig. 3. The describing function of a round-off quantizer with zero DC bias.
Fig. 4(a) shows a simulation of the transient response of
a digitally controlled PWM converter. The resolution of the
DPWM module,
Æ
ÔÛ
Ñ
½¼
bits, is higher than the reso-
lution of the ADC,
Æ
bits, however steady-state limit
cycling is observed both before and after the load current step,
since no integral term was used in the control law. On the other
hand, in Fig. 4(b) an integral term is added to the control law,
and the steady-state limit cycling is eliminated.
IV. C
ONTROLLED
D
ITHER
The precision with which a digital controller regulates
Î
ÓÙØ
is determined by the resolution of the ADC. In particular,
Î
ÓÙØ
can be regulated with a tolerance of one