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Microsystems Technology Office Page 1
Approved for Public Release, Distribution Unlimited
Energy Starved Electronics
(ESE)
Dr. Robert Reuss
DARPA/MTO
Approved for Public Release, Distribution Unlimited Page 2
Approved for Public Release, Distribution Unlimited
Energy Starved Electronics:
Wide Dynamic Range in Energy Consumption and
Performance
Requirements for Successful
Ultra Low-voltage Operation:
Architectures, circuits and devices
to reduce power consumption by
>100X yet mitigate throughput loss in
deep sub-threshold operation
Reliable operation with highly
variable device components
Wide-dynamic voltage range
capability to allow high performance
operation when needed
0
0.2
0.4
0.6
0.8
1
10
8
10
6
10
4
10
2
10
0
Normalized I
D
Normalized V
GS
Subthreshold Operation:
Low performance, minimum
energy, long operation life
Normal Operation,
Strong Inversion
: fast, high-energy, high performance
Unite the regions
From EETimes Feb. 2005
A paper from MIT may introduce a whole new
metric: lowest operating voltage. By aggressive
use of voltage-frequency scaling, subthreshold
circuit operation and supply voltage dithering,
the team was able to keep an adder circuit
operating over the full range from 1.1 V to under
300 mV.
This appears to be the lowest reported
operating voltage for a digital circuit at the
conference.
1 E -1 1
1 E -1 0
1 E -9
1 E -7
1 E -6
1 E -5
1 E -4
1 E -3



Tot
a
l Power
(W)
D e la y (s e c )
V
dd
= 1.0V
30x delay penalty
300x power
savings
2.2
µ
W
V
dd
= 0.3V
700
µ
W Page 3
Approved for Public Release, Distribution Unlimited
Price to Pay at Low Voltages
0
10
20
30
40
50
60
70
80
0
0.2
0.4
0.6
0.8
1
V
dd
(V)
StdDev/Mean (%)
Variability
0
0.2
0.4
0.6
0.8
1
1.2
10
15
10
14
10
13
10
12
V
DD
(V)
E/op (J)
Gate Leakage Energy
Total Leakage
Energy
Total Energy
Switching Energy
Delay of logic increases, which must be compensated for through
architecture optimization (e.g., parallelism and voltage dithering)
Leakage energy increases at extremely low voltages
Increased variability requires wider margins, reduced performance Page 4
Approved for Public Release, Distribution Unlimited
Power Reduction with Sub-threshold
Operation Optimization
Dev/Ckt/Arch Optimization is needed to achieve
target throughput using sub-threshold logic
Throughput
Power
Sub-threshold
Operation
Device
Optimization
Power Ceiling
Circuit/Architecture
Optimization
Duty Cycle
& Sizing
Parallelism
Ultra Dynamic
Voltage Scaling
Conventional
operation
Back Up
Back Up
Back Up Page 5
Approved for Public Release, Distribution Unlimited
Library for ULP Operation Some cells fail
above the
minimum energy
point Fixing them by
changing the sizes
increases
switched
capacitance, but
allows lower VDD
operation What cells are
optimal for a
certain design?
c
cn
D
c
cn
cn
c
cn
c
Q
Qn
c
cn
D
c
cn
cn
c
cn
c
Q
Qn FS Corner (strong NMOS,
weak PMOS) N3 cannot
hold a 1 when c=0 SF Corner (weak NMOS,
strong PMOS) N1
cannot hold a 0 when c=1
N1
N1
N3
N2
N3
N2
CLK
VD
D
V
BAT
VREF
EN
A
B
LE
ENERGY SENSOR
CIRCUITRY
DIGITAL
CIRCUIT
CRITICAL
PATH
REPLICA
ERROR
DETECTION
INCREASE
CRITICAL
PATH
DEPTH
Continuous feedback of energy/ power used to
set minimum energy point.
Total Savings can
increase dramatically
depending on Activity
7600X Savings
Min Energy Point 40X Savings over
nominal case
Back
0
5
10
15
20
0
0.1
0.2
0.3
0.4
0.5
Cell
Lowest working V
DD
(V)
TT
FS
SF Page 6
Approved for Public Release, Distribution Unlimited
Making Use of Parallelism
Ultra-low power circuits will require parallelism to make up for longer switching delays.
How many extra devices are needed?
Back
Model using power law function:
Performance = (Device count) / delay
If = 2
, then too much parallelism makes
things worse.
If = 1
, then parallelism works effectively.
What types of computations/tasks can best utilize parallelism?
1
1 0
1 0 0
1 0 0 0
C i r c u i t s ~ D i e C o s t
0 . 0 0 1
0 . 0 1
0 . 1
1
1 0
C
L i n e a r
3 / 2 P o w e r
2 P o w e r
1 . 5 v
0 . 7 v
0 . 3 v
1 0 % A c t i v i t y , V t = 0 . 3 V
Normalized Power = 1.0 = 1.5 = 2.0
V
DD
decreasing
1.77 nJ
2.47 nJ
19.1 nJ
Energy
/Operation
111k
450 mV
22 kHz
+ Sub-CMOS
86k
400 mV
22 kHz
+ Sub-Pseudo
NMOS
31k
650 mV
748 kHz
+ Sub-CMOS
# of
Transistors
Vdd
Clock
frequency
Implementation Parallel architecture lowers the clock rate, reduces power dissipation by 87% Pseudo NMOS logic styles provides another 28%reduction Page 7
Approved for Public Release, Distribution Unlimited
Ultra-Dynamic Voltage Scaling
10
5
10
4
10
3
10
2
10
1
10
0
10
6
10
5
10
4
10
3
10
2
10
1
10
0
Rate (normalized frequency)
Normalized Energy per sample (measured)
No dithering
ideal DVS
Dithered
1.1V, 340MHz
0.8V, 100MHz
0.5V, 2.4MHz
DVS
Time Constraint
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
Rate (normalized frequency)
Normalized Energy
Max rate
Sleep
Dynamic Voltage Scaling with
infinite levels
saves
energy per sample when the workload varies
Voltage
Scaling/Dithering
V
DD
H
V
DDL
Unit 1
Unit 3
Unit 2
Bus
Only two power supplies
needed for all blocks
Back
Closer to ideal over full range
Choose dithered voltages to match application of interest
Approve for Public Release, Distribution Unlimited Page 8
Approved for Public Release, Distribution Unlimited
Shaving Voltage Margins with EC Goal: reduce voltage margins with in-situ error detection and
correction for delay failures Proposed Approach: Tune processor voltage based on error rate Eliminate safety margins, purposely run below critical
voltage Data-dependent latency margins Trade-off: voltage power savings vs. overhead of
correction
0 . 8
1 . 0
1 . 2
1 . 4
1 . 6
1 . 8
2 . 0
0
2 0
4 0
6 0

S u p p l y V o l t a g e
Perc
en
tage Err
o
r
s
Traditional
DVS
Zero margin
Sub-critical
18x18-bit Multiplier Block at 90 MHz and 27 C
0.0000000%
0.0000001%
0.0000010%
0.0000100%
0.0001000%
0.0010000%
0.0100000%
0.1000000%
1.0000000%
10.0000000%
100.0000000%
1.14
1.18
1.22
1.26
1.30
1.34
1.38
1.42
1.46
1.50
1.54
1.58
1.62
1.66
1.70
1.74
1.78
Supply Voltage (V)
E
r
ro
r ra
t
e
random
Zero-margin
@ 1.54 V
Safety-margin
@ 1.63 V
Environmental-margin
@ 1.69 V
35% energy savings with 1.3% error
30% energy saving
22% saving
once every 20 seconds!
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