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Swaroop Ghosh Swaroop Ghosh







EDUCATION
PhD [2004-present]: School of ECE, Purdue University, IN, USA
Expected Graduation: May 15, 2008
Primary Research Area:
VLSI Circuit and Micro-architecture
Secondary Research Area:
Microelectronics and Nanotechnology
Research Advisor:

Prof. Kaushik Roy
Thesis: Integrated Fault-aware Adaptive Design and Self-Calibration Methodology for Low-Power and
Fault-Tolerant Nano-scale Systems
Graduate Courses: Solid State Devices, Computational Models and Methods, Advanced VLSI Design, Advanced VLSI Devices,
Digital Signal Processing, Introduction to complex analysis, Advanced linear algebra
Master of Science [2002-2004]: ECECS Department, University of Cincinnati, OH, USA
Primary Research Area:
VLSI Design and Testing
Secondary Research Area:
Low Power Design
Research Advisor:

Prof. Wen-Ben Jone
Thesis: Scan Chain Fault Identification using Weight-based m-out-of-n Codes
Graduate Courses: Design and analysis of algorithms, Introduction to Operating System, Physical VLSI design, VLSI system
design, Automata and formal languages, VLSI design and automation, Low Power VLSI design, Topics in VLSI design, VLSI
testing and validation, Intro to Computer Architecture
Bachelor of Technology [May 2000]: Indian Institute of Technology, Roorkee, India
Major:

Electrical Engineering
Thesis Advisor:
Prof. H. K. Verma and Prof. Vinod Kumar
Thesis: Design and Development of Remote Data Acquisition Module

RESEARCH INTERESTS
Low-power, fault tolerant and adaptive system design for nanoscale technologies.
1.

Modeling of failures at system level and providing fault tolerant, adaptive solutions to avoid the failures or compute in
presence of defects.
2.

Design methodologies to address power and process variation tolerance in logic circuits and embedded memories.
On-chip calibration, diagnosis and self-repair for improving reliability and yield
1.

Developing process sensors to detect/localize failures and apply on-chip corrective steps (adaptive clocking/source
biasing/adaptive voltage scheduling) to avoid the failures.
2.

Design-for-test methodologies to reduce test cost and improve yield.
Hybrid systems using emerging low-cost, low-power nano-electronic devices
1.

Optimization of nano-devices and developing compact models for circuit simulation.
2.

Application of the optimized devices to create hybrid and reconfigurable system for low power, fault tolerance, and on-line
test/verification.
Non-silicon nano-electronics and application to bio-implantable devices
1.

Novel biologically-inspired computing platforms for robust and low-power system design.
2.

Bio-implantable, miniature, ultra low-power devices for medical applications.

WORK EXPERIENCE
June-August 2007: Co-op engineer at Advanced Micro Devices (AMD) Inc, Sunnyvale, CA
1.

Memory testing at the RTL level for AMDs upcoming flagship processor.
2.

Scan partitioning to reduce scan power and supply voltage droop
May-August 2007: Summer intern at Intel Corporation, Portland, OR
1.

Sleep transistor variability analysis in L2-cache in 65nm process and its test implications.
August 2000-July 2002: VLSI design Engineer at Mindtree Technologies, Bangalore, India
1.

Design and test of Bluetooth Baseband Controller
PhD Candidate
School of Electrical and Computer Engg.
Mail Box 192, EE Bldg
Purdue University
West Lafayette, IN 47907-1285

Phone (H): 765-494-3372
Phone (C): 765-426-8700
Fax: 765-494-3371
Email: ghosh3@purdue.edu
URL: www.cobweb.ecn.purdue.edu/~ghosh3
2.

Distance measurement mode implementation in Baseband Controller
3.

Design and test of AHBC (Advance High Performance Bus Controller) Arbiter

TEACHING EXPERIENCE
Fall 2004-Spring 2005: Teaching Assistant for the undergraduate (senior year) course Introduction to electronic design
and analysis.
Course Content: basic electrical characteristics of common semiconductor devices (pn-junctions, MOSFETs, and BJTs),
analyze/design of D.C. bias circuits, utilizing D.C. and A.C. models of semiconductor devices in both analysis and design, single and
multistage amplifiers at low, mid and high frequencies, CAD tool (e.g., SPICE) for circuit analysis and design
Responsibilities: helping/teaching students, recitations once a week, prepare exams, quizzes, homeworks/solutions.
RESEARCH EXPERIENCE
Ph.D. Dissertation
Goal: Low-power and fault-tolerant nano-scale systems in presence of process variation and high defect densities.
Solution Strategy: Integrated fault-aware adaptive design and self-calibration methodology. The pre-Silicon fault-aware design ensures
low power operation under process variation. Furthermore, the design also keeps options of post-Silicon tuning of certain parameters for
adapting the failures if manufacturing defects are being detected in manufacturing test. In contrast to conventional low power fault
tolerant techniques, our design philosophy achieves highly reliable nano-scaled systems while staying under the power/performance
envelope. To further improve the reliability of the system, we use 3D hybrid technology with integrated low cost reconfigurable test
circuits designed using TFT. The TFT test circuits reduce the test overhead from Silicon die and monitor the critical sections of system
for online test and verification. This approach is elucidated as follows:





Fault-Aware Low-Power Adaptive Design Using Critical Path Isolation for Timing Adaptiveness (CRISTA)
1.

CRISTA methodology to isolate critical paths, make them predictable and avoid the possible errors by adaptive clock stretching.
CRISTA is used for correct computation under aggressive supply scaling in order to achieve low power operation. The CRISTA
design also enables post-Silicon self-correction.
2.

Employed CRISTA at the micro-architectural level (both In-Order and Out-Of-Order processor) to obtain low power and robust
pipeline designs.
3.

Designed hybrid adders and multipliers that further leverage CRISTA for low power dissipation under aggressive voltage scaling
at rated frequency. These hybrid units can be a part of execution units of high speed, low power, and variation-tolerant
processors.
4.

Designed a
test chip in IBM 130nm technology
to implement a two-stage low voltage pipeline in order to demonstrate the
feasibility of CRISTA under process variation.





Self-Calibrating Systems for Fault Tolerance
1.

Pre-Silicon design using CRISTA with isolated critical paths. If manufacturing test or on-chip speed binning suggest failure of
critical paths due to bridging defects then adaptive clock stretching is enabled to avoid delay failures. Designed a
test chip (IBM
130nm technology)
of built-in delay sensor for efficient speed binning.
2.

Developed a fault tolerant scheme that can leverage the inherent redundancy present in high speed arithmetic units in time
efficient manner to compute in presence of faults. The proposed methodology can used to design fault tolerant pipelines in high
performance systems.
3.

Employed CRISTA to design low-overhead temperature-adaptive systems. The supply voltage is dynamically scaled during
die-overheating while maintaining the rated clock frequency. The delay failures at scaled supply are adaptively tolerated by
adaptive clock stretching
4.

Exploiting the above methodology for successful prevention of die-overheating while maintaining rated frequency and tolerance
to delay failures at micro-architectural level (In-order processors). A prototype of high speed temperature tolerant pipeline with
temperature sensor for adaptive supply scaling is in progress.
5.

Developed an adaptive source biasing system and auto-repair scheme for low power and fault tolerant cache. Performed sleep
transistor variability analysis in L2 cache of Intels 65nm processor and explored its test implications. The optimal choice of
adaptive source biasing and body biasing to reduce power with robustness to failures is in progress.





Low Cost, Reconfigurable and Hybrid Electronic System Using Poly-Si Thin-Film Transistors
1.

Developed optimized TFT devices and SPICE compatible models for low-cost and ultra low-power digital operation. Using this
setup we simulated basic logic building block for power/performance estimation.
2.

Developed a low cost, generic and fully reconfigurable hybrid 3-D integrated system using Thin-Film-Transistors for test cost
reduction, improved controllability/observability, online test and verification. The test architecture can be configured as any
DFT/BIST or sensors and integrated with bulk-Si to create a hybrid system for improving the reliability of the underlying Silicon
die.





Other Projects
1.

Developed an integrated tester-on-chip consisting of low overhead delay sensors to improve the test coverage, test time and
delay fault diagnosis. The delay sensors are also used for fast speed binning of high performance dies.
2.

A novel CAD framework using Shannon expansion and dynamic supply gating to improve test power, IDDQ testability, test
cost and parametric yield. M.S. Dissertation
Goal: Scan Chain Fault Identificati