r most DDR appli-
cations. Load regulation meets the JEDEC spec, VTT =
VREFOUT ± 40mV.
The FAN1655 includes a buffered reference voltage
capable of supplying up to 5mA current. On-chip thermal
limiting provides protection against a combination of
power overload and ambient temperature that would
create an excessive junction temperature. A shutdown
input puts the FAN1655 into a low power mode.
The FAN1655 regulator is available in a power-enhanced
eTSSOP-16, standard SOIC-14, and an 8-Lead MLP
package.

Features

Sinks and sources 2.1A continuous, 3A peak

0 to +125°C operating temperature range

5mA Buffered VREFOUT = VDDQ/2

Load regulation: VTT = VREFOUT ± 40mV

On-chip thermal limiting

Low Cost SO-14, Power-Enhanced eTSSOP or
8-pin 5x6mm MLP packages

Low-Current Shutdown Mode

Output Short Circuit Protection

Applications

DDR Terminator VTT supply

Ordering Information
Block Diagram

Part Number
Temperature Range
Package
Packing

FAN1655M
0°C to 125°C
SOIC-14
Rails
FAN1655MX
0°C to 125°C
SOIC-14
Tape and Reel
FAN1655MTF
0°C to 125°C
eTSSOP-16
Rails
FAN1655MTFX
0°C to 125°C
eTSSOP-16
Tape and Reel
FAN1655MPX
0°C to 125°C
MLP-8
Tape and Reel
VSS
VSS
VSS
+ VTTSENSE
VTTFORCE
VTTFORCE
+ VDD
VDD
VDD
SHDN
VDDQ
200k
200k
FAN1655
VSSQ
VREFIN
VREFOUT
2

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Pin Assignments
Pin Denitions

Pin
Pin Name
Pin Function
MLP
eTSSOP
SOIC-14

1, 4
1, 2, 7
1, 2, 7
VDD
Input power for the LDO.
2, 3
3, 6
3, 6
VTTFORCE
The VTT output voltage.
PAD
4, 5, 8
4, 5, 8
VSS
IC Ground.
5
10
9
VTTSENSE
Feedback for remote sense of the VTT voltage.
11
10
VREFIN
Alternative input for direct control of VTTOUT and
VREFOUT.
6
12
11
SHDN
Shutdown. This active low shutdown turns off both VTT and
VREFOUT. This pin has an internal pull-down, and must be
externally driven high for the IC to be on.
13
12
VSSQ
Signal Ground.
7
14
13
VREFOUT
Buffered Voltage Reference Output.
8
15
14
VDDQ
VDDQ Input. Attach this pin to the VDDQ supply to generate
VTT and VREFOUT.
9, 16
NC
No Internal Connection
PAD
PAD
Connect PAD to Vss Ground Plane
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
FAN1655
NC
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
NC
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
VSS
14
13
12
11
10
9
8
1
2
3
4
5
6
7
FAN1655M
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
VSS
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
VDDQ
VREFOUT
SHDN
VTTSENSE
VDD
VTTFORCE
VTTFORCE
VDD
GND
1
2
3
4
8
7
6
5
16-Lead Plastic eTSSOP-16 JC
= 4C/W*
*Thermal impedance is measured with the power
pad soldered to a 0.5 square inch copper area.
The copper area should be connected to Vss
(ground) and positioned over an internal power
or ground plane to assist in heat dissipation.
14-Lead Plastic SOIC JC
= 37C/W, JA
= 88C/W
8-Lead MLP Package (5x6mm) JC
= 4C/W, JA
= 34C/W
as measured on FAN1655MP Eval Board
3

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Typical Application

Figure 1. (eTSSOP pinout shown)

Typical Performance Characteristics
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
100
µ
F
6V
10
µ
F
GND
VDD
1nF
(connect to VTTFORCE
at the load)
VTTSENSE
470
µ
F
10
µ
F
VTTFORCE
1nF
GND
VREFOUT
SHDN
VDDQ
10k
FAN1655
1.240
1.245
1.250
1.255
1.260
-3000
-2000
-1000
0
1000
2000
3000
V
TT
Load Current (mA)
V
TT
OUTPUT (V)
-40
-20
0
20
40
60
80
Quiescent Current vs. Temperature
QUIESCENT CURRENT (mA)
AMBIENT TEMPERATURE

(C)
4.5
3
0
1.5
-60
100 120
140
6
7.5
9
-5
-4
-3
-2
-1
0
1
V
REF
Output Change vs. I
REF V
REFOUT
(mV)
V
REF
LOAD CURRENT (mA)
0.5
0
-1.0
-0.5
-6
2
3
4
1.0
5
6
V
DD
= V
DDQ
= 2.5V
T
A
= 25C
1.0
10.0
100.0
1
1.5
2
2.5
3
Peak Load Current (A)
Current Pulse Duration (S)
T
A
=25
°
C
T
A
=70
°
C
Figure 2. Quiescent Current vs.
Ambient Temperature
Figure 3. Reference Output
Load Regulation
Figure 4. V
TT
Load Regulation
Figure 5. Maximum Non-Repetitive Output
Current vs. Pulse Width
(FAN1655M SO-14 Package)
4

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics

(VDD = VDDQ = 2.5V ± 0.2V, and T

A

= 25C using circuit in Figure 1, unless otherwise noted.)
The denotes specications which apply over the specied operating temperature range.
Supply Voltage VDD, VDDQ
6V
Junction Temperature, T

J

150C
Storage Temperature
-65 to 150C
Lead Soldering Temperature, 10 seconds
300C
Power Dissipation, P

D

FAN1655M (SOIC-14)
1.4W
FAN1655MTF (e-TSSOP)
FAN1655MP (MLP)
See Power Dissipation
and Derating

Parameter
Conditions
Min.
Typ.
Max.
Units

Supply Voltage VDD
2.3
2.5
3.6
V
Supply Voltage VDDQ
2.2
2.5
3.0
V
Ambient Operating Temperature
0
125
C
VREFIN
1.1
1.25
1.5
V

Parameter
Conditions
Min.
Typ.
Max.
Units

VTT Output Voltage
I

OUT

= 0A, VREFIN = open
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
I

OUT

= ±2.1A, VREFIN = open
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V



1.135
1.235
1.335
1.110
1.210
1.310
1.150
1.250
1.350
1.150
1.250
1.350
1.165
1.265
1.365
1.190
1.290
1.390
V
V
V
V
V
V
VTT Output Slew Rate
Cload = 10µF
0.3
V/µS
VTT Leakage Current
SHDN = 0V -50
50
µA
VTT Current Limit
±3.1
A
VREFIN Input Impedance
100
K

VREFOUT Output Voltage
No load
VREFIN = 1.150V
VREFIN = 1.250V
VREFIN = 1.350V



1.145
1.245
1.345
1.150
1.250
1.350
1.155
1.255
1.355
V
V
V
VREFOUT Output Current
VDDQ = 2.3V -5
5
mA
VREFOUT Leakage Current
SHDN = 0V -10
10
µA
SHDN Logic High 1.667
V
SHDN Logic Low 0.800
V
IDD Supply Current
No load, SHDN = 2.7V 7.5
20
mA
VDDQ Leakage Current
SHDN = 0V 6
10
µA
VDD Leakage Current
SHDN = 0V 3
50
µA
SHDN Input Current
SHDN = 2.7V 50
75
µA
Over-Temperature Shutdown
155
C
Over-Temperature Hysteresis
30
C
5

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Applications Information

Output Capacitor selection

The JEDEC specication for DDR termination requires
that VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay
within the 40mV window, the load step due to the load
transient current dropping across the output capacitors
ESR should be kept to around 25mV: where ESR <

is given in m

, and

I is the maximum load current.
For example, to handle a 3A maximum load transient,
the ESR should be no greater than 8m

. Furthermore,
the output capacitor must be able to hold the load in
spec while the regulator recovers (about 15µS). A mini-
mum value of 470µF is recommended.
The FAN1655 requires a minimum of 100µF of input
capacitance with a maximum ESR value of 100m

to
insure stability.

Power Dissipation and Derating

The maximum output current (sink or source) for a 1.25V
output is:
where P

D(MAX)

is the maximum power dissipation which
is:
where T

J(MAX)

is the maximum die temperature of the IC
and T

A

is the operating ambient temperature.
FAN1655 has an internal thermal limit at 150°C, which
denes T

J(MAX)

. For the SOIC-14 package,

JA

is given
at 88°C/W. Using equation 2, the maximum dissipation
at T

A

= 25°C is 1.4W, which is its rated maximum dissi-
pation.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the
package bottom. For maximum dissipation, this pad
should be soldered to the PCB copper, with as much
copper area as possible surrounding it to cool the pack-
age. Thermal vias should be placed as close to the ther-
mal pad as possible to transfer heat to other layers of
copper on the PCB. With large areas of PCB copper for
heat sinking, a

JA

of under 40°C/W can easily be
achieved.
25 I
------
I
OUT MAX
(
)
P
D MAX
(
)
1.25
----------------------
=
P
D MAX
(
)
T
J MAX
(
)
T
A
JA
----------------------------------
=
6

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Mechanical Dimensions

16-Lead eTSSOP
6.4
5.0
±
0.1
0.10 TYP
4.4
±
0.1
7.72
4.16
3.40
4.00
(1.78)
0.42 TYP
0.65 TYP
1.7 MIN
1.5 MIN
0.25
SEATING PLANE
SEE DETAIL A
DETAIL A
(1.00)
0.75
0.45
GAGE PLANE
LAND PATTERN RECOMMENDATION
0
°
8
°
R0.09MIN
12
°
TOP & BOTTOM
-A-
-B-
0.65 TYP
0.10
C B A
M
-C-
3.2
(0.90)+0.15
0.10
(0.090.20)
(0.190.30)
0.10
±
0.05 TYP
1.2 MAX
PIN #1 IDENT.
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT,

DATED 10/97.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND THE BAR EXTENSIONS.
D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
BOTTOM VIEW
0.2
ALL LEAD TIPS
ALL LEAD TIPS
C B A
0.1
1
8
1
1
8
8
9
16
9
9
16
16
C
7

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator

Mechanical Dimensions



14-Lead SOIC

Notes:

1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990.
2. All dimensions are in millimeters
3. Standard lead finished
200 microinches / 5.08 microns min.
Lead/Tin (solder) oncopper
S8.71-8.51;
S1.27-0.40;
S8-0
S0.50-0.25;X45
S1.75-1.35;
S0.25-0.10;z
7.62
S6.20-5.80;
1.27
S0.51-0.35;
S4.00-3.80
7
6
5
4
3
2
1
14
13
12
11
10
9
8
S0.25-0.19;
SEATING PLANE
0.50
1.00
1.27
7.62
LAND PATTERN RECOMMENDATION
5.75
8

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FAN1655 Rev. 1.1.5

F
AN1655 3A DDR Bus
T
ermination Regulator
Mechanical Dimensions