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Power and Control in Networked Sensors Power and Control in Networked Sensors
E. Jason Riedy
ejr@cs.berkeley.edu
Robert Szewczyk
szewczyk@cs.berkeley.edu
11 May, 2000
Abstract
The fundamental constraint on a networked sensor is
its energy consumption, since it may be either im-
possible or not feasible to replace its energy source.
We analyze the power dissipation implications of im-
plementing the network sensor with either a central
processor switching between i/o devices or a fam-
ily of processors, each dedicated to a single device.
We present the energy measurements of the current
generations of networked sensors, and develop an ab-
stract description of tradeos between both designs.
1
Introduction
Over the last few decades, Moores Law enabled
the hardware engineers to put a substantial amount
of computation and storage into increasingly smaller
packages. Additionally, advances in CMOS process-
ing and MEMS research make it possible to construct
a low-cost networked sensor. In the near future, re-
searchers predict that it will be possible to integrate
communication, power sources, sensors and actuators
with computational elements in a mm
3
[11].
Energy stored within each networked sensor is the
most precious resource, so both the hardware archi-
tecture and the software system should be optimized
for its usage. Each sensor has a limited energy source,
and replenishing this energy source may be either im-
possible (no physical access to the device) or not eco-
nomically viable (the maintenance cost can exceed
the sensor cost by orders of magnitude). Thus the en-
ergy eciency is probably the most important metric
against which the architectural choices must be eval-
uated.
A typical desktop PC contains many dierent pro-
cessing elements: besides the CPU, there are many
dedicated i/o processors for handling graphics, net-
work trac, or hard disk requests. These dedicated
i/o
processors were added in order to enhance the
performance of the system. In contrast, the current
generation of the networked sensor system looks more
like primitive home computer system from the late
70s: there is a single processor handling all the i/o
devices. The architects of the networked sensor will
sooner or later face a design dilemma: should there
be a dedicated processing element for each i/o device
or should the management of the i/o devices be cen-
tralized? How should these decisions be evaluated?
What are the fundamental tradeos between these
design alternatives?
In this paper we compare and analyze two architec-
tures for networked sensors: one based around a sin-
gle CPU handling multiple i/o devices, and one based
around two general purpose processors: one handling
the wireless communication system, and one handling
other i/o devices.
In general the power dissipation within a system is
proportional to frequency. In a system with real-time
deadlines, assigning the tasks to dedicated processors
implies that the individual processors will be able to
run at a signicantly lower frequency. Lowering the
frequency can lead to lowering the operating voltage
of the component. These two factors could yield sub-
stantial power savings. Furthermore, since the in-
dividual components might be tuned to meet their
deadlines just in time, they would not waste any en-
ergy in the idle states, whereas the scheduling of tasks
on a single processor might require that this processor
spends a portion of time idle.
These potential savings need to be balanced against
several factors: the communication between the pro-
cessors will almost certainly not be free, there typi-
cally is a xed cost associated with having an extra
component. Allocating tasks to processors is quite
similar to a packing problem. Depending on the gran-
ularity of tasks and a particular split, multiple pro-
cessors allocated to the problem might have to run
at either higher or lower cumulative frequency than
a single processor allocated to the task.
1 In this paper, we examine the implications of both
the single and multiple processor architectures on
the power dissipation within the system. We ana-
lyze both design styles in terms of abstract models,
and compare these models with the measurements
of a real system: a prototype networked sensor [9]
running TinyOS [6]. The rest of this paper is orga-
nized as follows. Section 2 introduces simple models
of hardware and software of the networked sensor and
Section 3 presents a particular implementation of a
networked sensor used to ground our empirical study.
Section 4 analyzes the power consumption of a single
processor system: we present a set of detailed energy
measurements of the single processor design in Sec-
tions 4.1 and 4.2, and analyze this data in abstract
terms in Sections 4.3 and 4.4. Section 5 extends this
analysis to systems with multiple processors. In Sec-
tion 6 we describe the related work, and conclude in
Section 7.
2
Architecture Model
To draw sound general conclusion about the power
analysis in networked sensors we need to be able to
abstract the observations of our particular hardware
and software system. In this section we present the
models of both hardware and software.
2.1
Task Model
A light-weight networked sensor is not expected to
be a general purpose computing device. Its goals are
to collect readings, process them slightly, and com-
municate readings with other sensors. For example,
a node may take three temperature readings, average
them, and trade averages with its neighbors. These
goals can be subdivided into various tasks, and the
tasks recur periodically and often be subject to real-
time constraints. Figure 1 shows a slice of a sensors
activities over a time span T . For analysis, we as-
sume that this time span is completely periodic; the
same tasks are executed in the same number for each
slice of length T .
Over the time T , the processor executes instructions
to control the devices and process readings. Let K be
the number of clock cycles occupied by instructions
during T . At a particular execution frequency of f
cycles per second, let be the utilization,
= K
f T .
(1)
T
Sensing (
), communicating (
), and processing
(
).
Figure 1: A networked sensor runs only a few classes of
tasks.
Note that K/T is a frequency itself, and at that fre-
quency the K cycles span the entire time T . This
frequency, f
m
, is the minimum frequency supporting
the given task set, and f = f
m
. Relating the fre-
quency and utilization will be useful for expressing
energy usage. When the processor is not busy, 1

of the time, it sits in a low-power idle or stop mode.
Scheduling general tasks to meet real-time con-
straints is a challenging topic in its own right, one we
leave to others [14, 3]. We assume that a scheduling
exists for any particular processor and device cong-
uration. This is not entirely realistic, but it allows us
to focus on power consumption rather than real-time
scheduling.
2.2
Hardware Model
To examine the power consumption in a small, net-
worked sensor, we also need a simple model of the
hardware. Figure 2 shows the block structure of sen-
sor nodes with dumb and intelligent i/o devices.
The devices are assumed to have power needs that do
not vary as instructions are partitioned between pro-
cessors. This is reasonable if the devices activity is
managed entirely with respect to real time, as when
a temperature sensor is be run every half-second for
a tenth of a second. The energy consumed by oper-
ating the sensor does not depend on the number of
processors or partitioning of tasks, and so we do not
complicate our analysis with these constants. We also
assume that the switching frequency of the processor
pins connected to the devices is determined by the
devices and is also constant for a task set.
Now how much energy is needed for the processing?
The energy consumed is the power over the time pe-
riod, E =
T
0
P dt. For the dc processing compo-
nents, P = IV , where the current I is a function
of f . We assume that voltage and frequency vary
indepently, e.g. we remain away from fundamental
cmos
limits.
We hold the voltage V constant, so
E = V
T
0
I(f )dt.
The task model, Section 2.1, separates the current
2 P
M
I/O
I/O
I/O
P
P
P
M
I/O
I/O
I/O
Figure 2: One central processor controls many dumb
devices, while each intelligent device has a dedicated
processor.
into an active current for T and an idle current for
(1
)T . This gives an energy consumption of
E = V T (I
active
(f ) + (1
)I
idle
(f ))
= V T (I
idle
(f ) + (I
active
(f )
I
idle
(f )))
= V T (I
I
(f ) + I
A
(f ))
(2)
over the recurrent period of length T . Here were de-
ned I
I
as the idle current, and I
A
as the extra cur-
rent needed over I
I
for executing instructions.