nt.
Power Management in Complex SoC Design
Power Management in Complex
SoC Design
Jim Flynn Senior IC Design Engineer, Synopsys Professional Services
Brandon Waldo Senior IC Design Engineer, Synopsys Professional Services
http://www.synopsys.com/sps
April 2004
�2004 Synopsys, Inc. �2004 Synopsys, Inc.
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The need to reduce power consumptionlong recognized as a significant design issuebecomes more
critical as larger, faster ICs go into portable applications. As a result, techniques for managing power
throughout the design flow are evolving to assure that all parts of the product receive power properly and
efficiently, and that the product is reliable. Techniques such as multi-voltage islands and dynamic scaling of
both clock frequency and threshold voltage help conserve battery power in portable applications, while
delivering high performance.
Perhaps more critically, increases in system-on-chip (SoC) size and speed have led to power consumption
challenges across a broad range of designs that have not been viewed traditionally as supply-limited. In
these designs, heat dissipation and reliability issues such as electromigration and IR drop have become
vitally important. (For information on dealing with power-related reliability issues, please consult the Synopsys
Professional Services White paper Design Planning Strategies to Improve Physical Design Flows
Floorplanning and Power Planning http://www.synopsys.com/cgi-bin/sps/wp/dps/paper1.cgi)
Power issues in mainstream deep submicron designs may limit functionality or performance and severely
affect manufacturability and yield. Higher power dissipation increases junction temperature, which slows
transistors and increases interconnect resistance. Design techniques aimed at improving performance may
therefore fall short if power is not considered. Lower-than-expected performance decreases device yield.
Additionally, higher power dissipation requires more system-level measures for thermal management. In
general, these power issues are increasing SoC and system costs. Managing power consumption at
appropriate points in the SoC design flow keeps these costs under control.
Where an SoC consumes power
The total power consumed by a chip equals dynamic power plus static power. Dynamic power is the power
consumed in switching logic states, both internal to the cells (internal power) and for driving the chips nets
and external loads (switching power):
Dynamic power = CV
2
F
where C is the load, V is the voltage swing and F is the number of logic-state transitions.
As semiconductor structures become smaller, device and interconnect capacitances decrease, allowing for
higher performance and lower power. Countering these factors are power increases due to larger designs
and higher switching rates.
Static power (leakage power) is consumed while transistors are not switching:
Static power = VI
STAT
Although transistors have some reverse-biased diode leakage from drain to substrate, the larger portion of
leakage power is due to the sub-threshold current through a transistor that is turned off. This sub-threshold
current results from the conduction between source and drain through the transistor channel.
The sub-threshold leakage current is problematic because it increases as transistor threshold voltages (V
th
)
decrease. In fact, the move to 130 nanometer (nm) and beyond may boost leakage power as high as 50
percent of the total chip power (Figure 1). Increased leakage power helps to exponentially increase reliability
related failures in chips (even in standby).
�2004 Synopsys, Inc.
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Figure 1: Increase in leakage powerBringing down transistor threshold voltages helps decrease dynamic power but increases
sub-threshold leakage current. A power-aware design flow is thus needed to meet timing requirements and keep power consumption
within acceptable limits. Source: Intel. Published in IC Insights Inc. 2003 Technology Trends.
As CMOS technologies scale down, the main approach for reducing power has been to scale down the
supply voltage V
DD
. Voltage scaling is a good technique for controlling a chips dynamic power because of
the quadratic effect of voltage on power consumption. However, just reducing the power supply degrades
circuit speed because the switching delay time is proportional to the load capacitance and the ratio V
th
/V
DD
.
To maintain sufficient drive strength for fast switching, V
th
must decrease in proportion to V
DD
. This relationship
leads to the leakage power increase. Fortunately, a power-aware design flow helps balance timing
requirements with various power goals.
Power solutions
The higher the level of design abstraction, the greater the influence on power consumption. At the system
and algorithm levels, for example, using a parallel approach rather than a serial implementation reduces
clock frequencies, which helps to decrease power consumption significantly. The lower power of the parallel
approach may come at the expense of somewhat greater area or slower performance.
To give an example of the effect of parallel vs. sequential architectures, in one chip that received data
samples serially, the samples were processed in parallel to reduce this logics clock speed from 80 to 10
MHz. Additionally, the supply voltage was reduced from 1.8V to 1.25V. The parallel processing logic was
much larger than the serial processing equivalent, but the logics reduced voltage and operating frequency
reduced the power consumption by 75 percent. This parallel approach was able to save power because
power has a squaring function to voltage and only a linear function for frequency and switching. In other
designs, the area penalty has been small but the power savings significant, so it is worth exploring the tradeoffs. �2004 Synopsys, Inc.
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Figure 2: In the context of the design flow, the potential for power savings and the accuracy of power estimates is greatest early in
the flow.
Figure 2 references several power optimization and analysis techniques that can be used throughout an
SoC design flow. The power solutions covered in this paper include:
I
Module clock gating
I
Multiple supply voltages
I
Multiple threshold voltages
I
Power optimization in synthesis, including RTL clock gating
Because techniques such as clock gating and dividing affect design for test (DFT), that topic is also
addressed. A brief design example at the end of the paper shows the benefits of combining dynamic
frequency and voltage scaling.
Power estimation and analysis
Over the course of the design flow, it is useful to estimate power consumption at four stages (Table 1). The
accuracy of the estimate improves at each stage as additional design and library information becomes available.
System Design
RTL Design
Floorplanning
Synthesis
Place and Route
Power Optimization
Architecture optimization
(e.g. parallel vs. serial)
Supply voltage scaling
Clock frequency scaling
Module clock gating
Voltage islands
Threshold voltage scaling
Power optimization in synthesis
RTL clock gating
Power Analysis
Power estimates based on
- Estimated gate counts
- Estimated activity
RTL power analysis based on
defined clocks and registers
- Estimated gate counts
- Realistic activity
Gate level power analysis
based on
- Actual gate counts
- Realistic activity
- Wireload models
- Final libraries
Gate level power analysis
based on
- Actual gate counts
- Realistic activity
- Accurate routing
- Final libraries �2004 Synopsys, Inc.
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Table 1: Four stages of power consumption estimation (Recommended).
When to perform the
How Gates are
How Load is
Estimation
estimation during
Calculated
Calculated
Tool(s) Used
1. Design/library exploration
Rough estimation
Unknown/In definition
Spreadsheet
2. Pre/early synthesis
Rough estimation
DC-Wire Load Models
Design Compiler,
Power Compiler
3. Post-synthesis
Accurate (placed)
Wire Load Models/SPEF
Power Compiler,
Physical Compiler,
PrimePower
4. Post-layout
Exact
Extracted SPEF
PrimePower
RTL power analysis
In the earliest stages of a design flow, power analysis provides rough estimates of a designs power
consumption. Libraries may not be selected yet, so library data may be limited. Before the library is
selected, a spreadsheet analysis can be used to reveal the best power-conscious libraries and design
architectures. After the library is selected, Design Compiler
�
and Power Compiler can be used instead of
the spreadsheet method or to supply values for use in the spreadsheets.
The power-analysis spreadsheet includes approximate gate counts, rough activity-per-block values, side-
by-side vendor �W/MHz data, and relative power estimates. The analysis at this point also helps to show
if a design consumes too much power to be practicalthus avoiding weeks of design effort to implement
a chip that will never be manufactured.
To use the spreadsheet analysis method, it is necessary to estimate each blocks gate count (number of
library cells of each type) and activity level. The amount of energy consumed by the switching of each cell
type is also needed; data from a library vendors manuals can be used to assign an appropriate power
value relative to speed (in �W/MHz). A blocks internal power consumption for a particular type of cell is
given by the equation:
Power consumption = Gate Count * �W/MHz * Activity * Frequency
Summing these power values for all the different types of cells in a block gives the blocks overall internal
active-power es