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32-Bit RISC MICROPROCESSOR TX39 FAMILY CORE ARCHITECTURE USER'S MANUAL
32-Bit RISC MICROPROCESSOR
TX39 FAMILY CORE ARCHITECTURE
USER'S MANUAL
Jul. 27, 1995
R3000A is a Trademark of MIPS Technologies, Inc.
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA
or others.
The products described in this document contain components made in the United States and subject to export control
of the U.S.authorities. Diversion contrary to the U.S. law is prohibited.
These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication
equipment, measuring equipment, domestic electrification, etc.).Please make sure that you consult with us before you
use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which
could have major impact to the welfare of human life (atomic energy control, airplane, spaceship, traffic signal,
combustion control, all type of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may
occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with
TOSHIBA,
©
1995 TOSHIBA CORPORATION
All Rights Reserved. CONTENTS
i
CONTENTS
Architecture
Chapter 1
Introduction---------------------------------------------------------------------------
3
1.1
Features ------------------------------------------------------------------------------
3
1.1.1
High-performance RISC techniques ---------------------------------------------------- 3
1.1.2
Functions for embedded applications--------------------------------------------------- 3
1.1.3
Low power consumption ------------------------------------------------------------------- 4
1.1.4
Development environment for embedded arrays and cell-based ICs ---------- 4
1.2
Notation Used in This Manual ---------------------------------------------------
5
Chapter 2
Architecture -------------------------------------------------------------------------
7
2.1
Overview------------------------------------------------------------------------------
7
2.2
Registers------------------------------------------------------------------------------
8
2.2.1
CPU registers--------------------------------------------------------------------------------- 8
2.2.2
System control coprocessor (CP0) registers ----------------------------------------- 9
2.3
Instruction Set Overview------------------------------------------------------------
10
2.4
Data Formats and Addressing ----------------------------------------------------
15
2.5
Pipeline Processing Overview-----------------------------------------------------
18
2.6
Memory Management Unit (MMU) -----------------------------------------------
19
2.6.1
R3900 Processor Core operating modes ----------------------------------------------- 19
2.6.2
Direct segment mapping -------------------------------------------------------------------- 20
Chapter 3
Instruction Set Overview------------------------------------------------------------
23
3.1
Instruction Formats ------------------------------------------------------------------
23
3.2
Instruction Notation ------------------------------------------------------------------
23
3.3
Load and Store Instructions -------------------------------------------------------
24
3.4
Computational Instructions---------------------------------------------------------
27
3.5
Jump/Branch Instructions ----------------------------------------------------------
32
3.6
Special Instructions ------------------------------------------------------------------
35
3.7
Coprocessor Instructions -----------------------------------------------------------
36
3.8
System Control Coprocessor (CP0) Instructions -----------------------------
38 CONTENTS
ii
Chapter 4
Pipeline Architecture-----------------------------------------------------------------
39
4.1
Overview--------------------------------------------------------------------------------
39
4.2
Delay Slot-------------------------------------------------------------------------------
40
4.2.1
Delayed load ----------------------------------------------------------------------------------- 40
4.2.2
Delayed branching---------------------------------------------------------------------------- 40
4.3
Nonblocking Load Function --------------------------------------------------------
41
4.4
Multiply and Mupliply/Add Instructions
(MULT, MULTU, MADD, MADDU)
--
41
4.5
Divide Instruction (DIV, DIVU) ----------------------------------------------------
42
4.6
Streaming-------------------------------------------------------------------------------
42
Chapter 5
Memory Management Unit (MMU) -----------------------------------------------
43
5.1
R3900 Processor Core Operating Modes --------------------------------------
43
5.2
Direct Segment Mapping -----------------------------------------------------------
44
Chapter 6
Exception Processing ---------------------------------------------------------------
47
6.1
Overview--------------------------------------------------------------------------------
47
6.2
Exception Processing Registers --------------------------------------------------
50
6.2.1
Cause register --------------------------------------------------------------------------------- 51
6.2.2
EPC (Exception Program Counter) register-------------------------------------------- 52
6.2.3
Status register --------------------------------------------------------------------------------- 53
6.2.4
Cache register --------------------------------------------------------------------------------- 56
6.2.5
Status register and Cache register mode bit and exception processing -------- 58
6.2.6
BadVAddr (Bad Virtual Address) register----------------------------------------------- 60
6.2.7
PRId (Processor Revision Identifier) register ------------------------------------------ 60
6.2.8
Config (Configuration) register ------------------------------------------------------------ 61
6.3
Exception Details ---------------------------------------------------------------------
63
6.3.1
Memory location of exception vectors --------------------------------------------------- 63
6.3.2
Address Error exception -------------------------------------------------------------------- 64
6.3.3
Breakpoint exception------------------------------------------------------------------------- 65
6.3.4
Bus Error exception -------------------------------------------------------------------------- 66 CONTENTS
iii
6.3.5
Coprocessor Unusable exception -------------------------------------------------------- 68
6.3.6
Interrupts ---------------------------------------------------------------------------------------- 69
6.3.7
Overflow exception --------------------------------------------------------------------------- 70
6.3.8
Reserved Instruction exception------------------------------------------------------------ 70
6.3.9
Reset exception ------------------------------------------------------------------------------- 71
6.3.10
System Call exception----------------------------------------------------------------------- 72
6.3.11
Non-maskable interrupt --------------------------------------------------------------------- 72
6.4
Priority of Exceptions ----------------------------------------------------------------
73
6.5
Return from Exception Handler ---------------------------------------------------
73
Chapter 7
Caches ----------------------------------------------------------------------------------
75
7.1
Instruction Cache ---------------------------------------------------------------------
75
7.2
Data Cache ----------------------------------------------------------------------------
76
7.2.1
Lock function ----------------------------------------------------------------------------------- 77
7.3
Cache Test Function-----------------------------------------------------------------
79
7.4
Cache Refill ----------------------------------------------------------------------------
80
7.5
Cache Snoop --------------------------------------------------------------------------
81
Chapter 8
Debugging Functions ----------------------------------------------------------------
83
8.1
System Control Processor (CP0) Registers -----------------------------------
83
8.2
Debug Exceptions --------------------------------------------------------------------
87
8.3
Details of Debug Exceptions-------------------------------------------------------
90
Appendix A