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Dual Triple DMOS Output Driver with Serial Input Control T6817 Features Three High-side and Three Low-side Drivers Outputs Freely Configurable as Switch, Half Bridge or H-bridge Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors 0.6A Continuous Current Per Switch Low-side: R
DSon
< 1.5 Versus Total Temperature Range High-side: R
DSon
< 2.0 Versus Total Temperature Range Very Low Quiescent Current I
S
< 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage and Overvoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail Serial Data Interface Daisy Chaining Possible SSO20 Package
1.
Description
The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technol-
ogy. It can be used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design is especially supportive of
H-bridges applications to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnosis functions and a very low quiescent current in
standby mode open a wide range of applications. Meeting automotive qualifications in
the area of conducted interferences, EMC protection and 2 kV ESD protection provide
added value and enhanced quality for the exacting requirements of automotive
applications.
Dual Triple
DMOS Output
Driver with
Serial Input
Control
T6817
4670DBCD04/07 2
4670DBCD04/07
T6817
Figure 1-1.
Block Diagram
HS1
HS2
HS3
DI
CLK
INH
DO
CS
OV
-
protection
UV
-
protection
V
S
V
S
Vcc
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
S
I
S
T
C
O
L
D
n.
u.
P
S
F
I
N
H
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
Fault
detect
Fault
detect
Fault
detect
Fault
detect
GND
GND
GND
GND
VS
Fault
detect
Fault
detect
LS1
LS2
LS3
VS
VCC
Thermal
protection
Osc
Control
logic
Vcc
Power-on
reset
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
2
4
3
5
18
12
14
16
8
15
17
13
1
10
11
19
6
7
GND
20 3
4670DBCD04/07
T6817
2.
Pin Configuration
Figure 2-1.
Pinning SSO20
GND
DI
CS
CLK
INH
VS
VS
LS3
n.c.
GND
GND
VCC
DO
LS1
HS1
LS2
HS2
GND
HS3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Table 2-1.
Pin Description
Pin
Symbol
Function
1
GND
Ground; reference potential; internal connection to pin 10, 11, 13 and 20; cooling tab
2
DI
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control
device, DI expects a 16-bit control word with LSB being transferred first
3
CS
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
4
CLK
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
5
INH
Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating
6, 7
VS
Power supply output stages HS1, HS2 and HS3
8
LS3
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
9
n.c.
Not connected
10
GND
Ground (see pin 1) be consistent
11
GND
Ground (see pin 1)
12
HS3
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
13
GND
Ground (see pin 1)
14
HS2
High-side driver output 2 (see pin 12) be consistent
15
LS2
Low-side driver output 2 (see pin 8)
16
HS1
High-side driver output 1 (see pin 12)
17
LS1
Low-side driver output 1 (see pin 8)
18
DO
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
19
VCC
Logic supply voltage (5V)
20
GND
Ground (see pin 1) 4
4670DBCD04/07
T6817
3.
Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
Data Transfer Input Data Protocol
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
OLD
SCT
SI
CS
DI
CLK
DO
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 3-1.
Input Data Protocol
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and overtemperature
shutdown in the output data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
n.u.
Not used
8
n.u.
Not used
9
n.u.
Not used
10
n.u.
Not used
11
n.u.
Not used
12
n.u.
Not used
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit and overvoltage shutdown (short
circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown
delay high/low = 14 ms/3.5 ms
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is
still powered) 5
4670DBCD04/07
T6817
Note:
Bit 0 to 15 = high: overtemperature shutdown
Table 3-2.
Output Data Protocol
Bit
Output (Status)
Register
Function
0
TP
Temperature prewarning: high = warning (overtemperature shut-down,
see remark below)
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
3
Status LS2
Description, see LS1
4
Status HS2
Description, see HS1
5
Status LS3
Description, see LS1
6
Status HS3
Description, see HS1
7
n.u.
Not used
8
n.u.
Not used
9
n.u.
Not used
10
n.u.
Not used
11
n.u.
Not used
12
n.u.
Not used
13
SCD
Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
14
INH
Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin 17). High = standby, low = normal operation
15
PSF
Power supply fail:

over- or undervoltage at pin VS detected
Table 3-3.
Status of the Input Register after Power on Reset
Bit 15
(SI)
Bit 14
(SCT)
Bit 13
(OLD)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
H
H
H
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
L
L
L
L
L
L
L 6
4670DBCD04/07
T6817
3.2
Power-supply Fail
In case of over- or undervoltage at pin VS, an internal timer is started. When the undervoltage
delay time (t
dUV
, t
dOV
) programmed by the SCT bit is reached, the power supply fail bit (PSF) in
the output register is set and all outputs are disabled. When normal voltage is present again, the
outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the
input register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current I
HS1-3
,
I
LS1-3
). If V
VS
-V
HS1-3
or V
LS1-3
is lower than the open-load detection threshold (open-load condi-
tion), the corresponding bit of the output in the out