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AP-211 Instantly Available PCI Card Power Management
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
9/99
1
Introduction
Today, PCs need to remain constantly connected to the outside
world, but at the same time consume minimum power. Even
when looking “idle”, it is still possible to receive a message
from the Internet or an incoming fax or phone call. The PC
must automatically go from “sleep” mode to “on” mode; in
other words, an “Instantly Available” PC (IAPC). The challenge
is to maintain a system‘s modem or Local Area Network
(LAN) connectivity on a desktop PC/workstation while at the
same time minimizing power consumption. These power
management features are called Wake-on-Ring (or Wake-
on-Modem), Wake-on-LAN, and Wake-on-PME (Power
Management Event).
The main qualities/benefits of such a system are:
•
Listening: available anytime to receive messages from
the outside world, and
•
Reacting: responding anytime to do a specific operation
(maintenance…), and
•
Saving energy and being silent in the idle mode.
The “OnNow” initiative by Microsoft® defined the new
requirements for the system that affect both software and
hardware aspects of the PC: Windows® operating system,
applications, device drivers, and hardware within the system.
All these elements must work together in order to provide a
fully transparent power management system. This note will
focus only on the hardware aspects.
ACPI System Design
An instantly available PC appears to be “off”, yet it can snap
back to its full ready state within seconds and respond to
the phone ringing in time to service the call.
In order to meet these requirements a recommendation, the
Advanced Configuration and Power Interface specification
(ACPI), has been defined by Intel®, Microsoft®, and
Toshiba®.
Instantly available motherboards include: ACPI BIOS, ACPI
chip set, and PCI slots that are compliant to the PCI-PM
specification. The Intel chip set supports the power
management features to define the ACPI sleep states and
also generates the signals to control power planes to turn
the main power supplies on and off.
The implementation includes multiple power sources and
uses separate power planes in the system. Each power source
is selected depending on the required state demanded by
the system, and one of the major requirements is to switch
between power sources continuously, automatically, and
without interruption.
The “sleep” state of an instantly available PC is called “Suspend
to RAM”. This is implemented by using:
•
split power planes in the system design, and
•
an auxiliary power source (V
AUX
) for dual mode power
distribution.
Let’s focus on the PCI (Peripheral Component Interface) cards,
where California Micro Device’s products have their primary
applications. By definition, all PCI add-on cards are connected
to the motherboard through the PCI bus. On the PCI
connector, several pins have been reserved in order to support
the instantly available functionality.
•
PME# (Power Management Event) pin (pin #A19) is
used to wake the system in response to a PCI power
management wake event such as the phone ringing.
•
3.3Vaux pin (pin #A14) is used to deliver the auxiliary
power of 3.3V to all the wake-up PCI cards in the system.
This power is always available to keep the card active
even when the rest of the PCI bus is without power.
Three different independent voltage sources are now available
on the PCI bus: 3.3V
AUX
, 3.3V
CC
, and 5V
CC
. In a power plane
partitioning system of an instantly available PC, the 3.3V
AUX
is
electrically isolated from the main PCI 3.3V rail at all times.
During normal operation, the 3.3V
AUX
supply remains on all
the time, while the other main supplies, 3.3V
CC
and 5V
CC
, can
be switched on and off as needed.
PCI Adapter Card Application
PCI Network Interface Cards (NIC) and modem cards are also
designed with split power planes. Thus, they are able to
operate in sleep mode with only the Vaux power supply and
still be able to wake-up the system.
Some NICs that operate in “Wake on LAN” mode get a 5V
standby through a cable that connects directly to a specific
header on the motherboard.
Chip Set Voltage
Today, PCI card chip sets or ASICs operate at a low voltage of
3.3V. That allows much lower power consumption than with
the previous 5V modem chips. However “older” PCs are still
operating at 5V and do not have any 3.3V
AUX
supply. “New”
PCI cards must be compatible with these systems still in service,
and therefore must regulate on board their own 3.3V supply
from the 5V. This is made possible by using California Micro
Devices’ SmartOR
™

power management products: the
CMPWR100 and CMPWR150. In addition, there is a
maximum current limitation of 375mA on the 3.3V
AUX
.
C0210699A
All trademarks are the property of their respective holders.
©1999 California Micro Devices Corp. All rights reserved.
P/Active
®
is a registered trademark and SmartOR™ is a trademark of California Micro Devices.
CALIFORNIA MICRO DEVICES
AP-211 9/99
2
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CALIFORNIA MICRO DEVICES
AP-211
Figure 1. CM PWR-100 Block Diagram
Power Requirements on V
AUX
In order to limit the power consumed by the system in the
“sleep” mode, each PCI card must reduce its current
consumption from the auxiliary power supply. The power
operating conditions are displayed below.
That means that each PCI add-in card’s load on 3.3V
AUX
must
not exceed 375mA. When the board is in a sleep state with
wake up event generation disabled, it must reduce its total slot
current to less than 20mA which can be done several ways:
•
internally disabling as much logic as possible on the
board, or
•
electrically isolating the 3.3
V
AUX
pin from the auxiliary
power plane of the board.
Dual Power Supply
A dual mode power supply is able to deliver the same reference
voltage from two separate tuned (load-wise) power sources.
For example, a main power source will provide a high capacity,
high efficiency 3.3V source for heavy “runtime” loads, and a
lower capacity auxiliary source, yet reasonably efficient, 3.3V
source for lightly loaded “sleeping” states. A voltage switch
is required in order to select between one of these two different
sources. This can be implemented with discrete Schottky
diodes, or more efficiently, with California Micro Devices’
power switch, the CMPWR025.
California Micro Devices has developed a family of SmartOR
TM
Power Management devices to address all these requirements
whose characteristics are summarized in Table 2 and will be
the primary focus of this application note.
Table 1. Power Requirements for V
AUX
Table 2. Summary of Power Management Devices
Figure 2. CM PWR-150 Block Diagram
In the next sections, we will discuss specific applications for
the CMPWR100 and CMPWR150. In order to facilitate the
design process, California Micro Devices has available a
SmartOR
TM
evaluation board for use in the lab and to facilitate
PCB layout.
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All these parts are general purpose smart voltage regulators
and/or switches. They can be used in PCI modem, PCI LAN
card, or dual power system applications.
Figures 1-3 below illustrate a simplified block diagram of
each of the power management devices.
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•
electrically isolating the 3.3
V
AUX
pin from the auxiliary
power plane of the board.
Figure 3. CMPWR025 Block Diagram 9/99
3
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CALIFORNIA MICRO DEVICES
AP-211
Vcc
output
Figure 5. Equivalent circuit with line parasitic
C
+
Power supply
R
s
R
t
L
t
V
cc_in
CM PWR-150
R
L
Hysteresis
Hysteresis is illustrated in Figure 4 and is defined as the
difference between the enabling threshold (when the regulator
turns on) and the disabling threshold (when the regulator
turns off). The hysteresis level sets up the maximum level of
acceptable noise or disturbance on V
CC
or V
AUX
. This is
particularly critical during power transitions.
As shown in Figure 5, the voltage seen by the device is given
by:
V
cc_in
= V
cc
– (R
s
X I) - (R
t
X I) – (L
t
X dI/dt)
Assuming an ideal situation where there is no parasitic
inductance, the hysteresis level should follow the equation
below.
V
hysteresis
>