mentation
maintains low power at high speed
l
Schmitt trigger inputs and CMOS
logic levels improve noise immunity
l
Simultaneously injects equal dead-
time in up to three output phases
l
Replaces 10-12 standard SSI/MSI
logic devices
l
Allows a wide range of PWM
modulation strategies
l
Directly drives high speed
optocouplers
Applications
l
1- and 3- Phase Motion Controls
l
1- and 3- Phase UPS Systems
l
General Power Conversion Circuits
l
Pulse Timing and Waveform
Generation
l
General Purpose Delay and Filter
l
General Purpose Three Channel
"One Shot"
In the IXDP630, deadtime programming
is achieved by an internal RC oscillator.
In the IXDP631, programming is
achieved by use of a crystal oscillator.
An alternative for both the IXDP630/
631 is with an external clock signal.
Because of its flexibility, the IXDP630/
631 is easily utilized in a variety of
brushed DC, trapezoidally commutated
brushless DC, hybrid and variable
reluctance step and other more exotic
PWM motor drive power and control
circuit designs.
This 5 V HCMOS integrated circuit is
intended primarily for application in
three-phase, sinusoidally commutated
brushless motor, induction motor, AC
servomotor or UPS PWM modulator
control systems. It injects the required
deadtime to convert a single phase leg
PWM command into the two separate
logic signals required to drive the upper
and lower semiconductor switches in a
PWM inverter. It also provides facilities
for output disable and fast overcurrent
and fault condition shutdown.
Block Diagram IXDP 630/IXDP 631 I - 15
© 1998 IXYS All rights reserved
IXDP630
IXDP631
Symbol
Definition
Maximum Ratings
min.
max.
V
CC
Supply Voltage
-0.5
7
V
V
IN
DC Input Voltage
-0.5
V
CC
+ 0.5
V
I
IN
DC Input Current
-1
1
mA
V
0
DC Output Voltage
0.5
V
CC
+ 0.5
V
I
0
DC Output Current
-25
25
mA
T
stg
Storage Temperature
-55
150
°
C
T
L
Lead Soldering (max. 10 s)
300
°
C
Recommended Operating Conditions
V
CC
Supply Voltage
4.5
5.5
V
T
J
Operating Temperature
-40
85
°
C
l
0
Output Current
-8
8
mA
f
OSC
Oscillator Frequency
0.001
16/24 MHz
Symbol
Definition/Condition
Characteristic Values
min.
typ.
max.
V
t+
Input Hi Threshold
3.6
2.7
V
V
t-
Input Lo Threshold
1.6
0.8
V
V
HYS
Hysteresis
1.1
V
I
in
Input Leakage Current
-10
10
µ
A
C
in
Input Capacitance
5
10
pF
V
oh
Output High Voltage l
o
= -8 mA
2.4
V
V
ol
Output Low Voltage l
o
= 8 mA
0.4
V
I
CC
Supply Current Outputs Unloaded
5
mA
I
CCQ
Quiescent Current Outputs
0.4
1
mA
Unloaded IXDP630
I
CCQ
Quiescent Current Outputs
1
10
µ
A
Unloaded IXDP631
DP630 Oscillator Section
C
OSC
Capacitor (RCIN to GND)
0.047
10
nF
R
OSC
Resistor (OSCOUT to RCIN)
1 1000
k f
OSC
Frequency Range
0.001 - 16
MHz
Initial Tolerance (f
OSC


1MHz)
5
%
Temperature Coefficient
-400
ppm/
°
C
DP631 Oscillator Section
f
OSC
Frequency Range
0.1-24
MHz
V
INH
Oscillator Thresholds (IXTLIN)
3.9
V
V
INL
0.8
V
External Oscillator
f
IN
Frequency Range (ODCOUT open)
0-24
MHz
t
SX
Set Up Time DATA-to-XTLIN
14
n
S
t
SC
Set Up Time DATA-to-OSCIN
22
ns
t
hold
Hold Time CLOCK-Data
0
ns
t
pdro
Propagation Delay RESET-to-OUTPUT
15
20
ns
t
pdeo
Propagation Delay ENABLE-to-OUTPUT
8
16
ns
Dimensions in inch (1" = 25.4 mm)
16-Pin Plastic DIP
t
pdeo
t
pdro
t
hold
t
SC
t
SX I - 16
© 1998 IXYS All rights reserved
IXDP630
IXDP631
Sym. Pin Description
GND
9 CIRCUIT GROUND - 0 Volts
RCIN 10 The first node of the clock
or
network. For the IXDP630, the
XTLIN
RC input is applied to RCIN. For
the IXDP 631, the crystal oscil-
lator is applied to XTLIN. If an
external clock is to be supplied
to the chip it should be connec-
ted to this pin.
OSC 11 This is the output node of the
OUT
oscillator. It is connected indi-
rectly to the RCIN or XTLIN pins
when using the internal oscillator
as described in the applications
information. It is not recommen-
ded for external use.
TL
12 After the appropriate delay, the
TU
13 external drive outputs (R,S, T) U
SL
14 are in phase with their corres-
SU
15 ponding inputs; (R,S, T) L are
RL
16 the complementary outputs.
RU
17
V
CC
18 Voltage Supply +5 V
±
10 %
Sym. Pin Description
R
1 R, S and T are the three single-
S
3 phase inputs. Each input is
T
5 expanded into two outputs to
generate non-overlapping drive
signals, RU/RL, SU/SL, and TU/
TL. The delay from the falling
edge of one line to the rising
edge of the other is a function of
the clock.
ENAR 2 High logic input will enable the
ENAS 4 outputs, as set by the proper
ENAT 6 input phase. The ENA (R,S,T)
signals control the drive output
lines. A low logic input will force
both controlled outputs to a low
logic level
OUT 7 High logic level will enable all
ENA
outputs to their related phase.
The OUTENA simultaneously
controls all outputs. Low input
logic level will inhibit all outputs
(low).
RESET 8 The RESET signal is active low.
When a logic low RESET is
applied, all outputs will go low.
After releasing the RESET
command within the generated
delay, the outputs will align with
the phase input level after the
programmed delay internal.
Pin Description
IXDP630
Pin Description
IXDP631
Waveforms
deadtime
deadtime
deadtime
deadtime
This diagram shows the normal
operation of the IXDP630/631 after the
RESET input is released. The
DEADTIME is the 8 Clock periods
between XU and XL when both XU and
XL are a "0". The length of the
DEADTIME is fixed at 8 times the
period of CLK.
The

diagram

shows

OUTENA

and ENAX
asynchronously forcing the XU Output
and the XL Output to the off state.
OUTENA will force all three channels to
the off state. ENAX (where X is one of
the three channels) will only force the
XU and XL Outputs of that channel to
the off state. Note that because ENAX
is asynchronous with respect to the
internal clock and deadtime counters,
when ENAX goes HI whatever state the
deadtime counter was in immediately
propagates to the output. This figure
also shows that noise at the XIN input
will be filtered before the XU Output or
XL Output will become active, which
may extend the deadtime.
Note: X = Any input, R, S or T.
noise
deadtime
deadtime I - 17
© 1998 IXYS All rights reserved
IXDP630
IXDP631
Application Information
Basic Operation
The IXDP630/631 Deadtime Genera-
tors are intended to simplify the
implementation of a single- or three-
phase digitally controlled power
conversion circuit. It replaces one to
three digital event counters (timer/
counters) in a microcontroller or DSP
implementation of a motor control, UPS
or other power system. In most cases
these timers are at a premium. They
must be used to calculate pulse width
on one to three independent modula-
tors,

set

interrupt

service

times,

generate
a real-time clock, handle communica-
tions timing functions, etc.
The input command on the R, S and T
inputs is first synchronized with the
internal oscillator. When an input
changes state, the on output is
switched off, and after a deadtime of
exactly 8 clock periods, the complimen-
tary output is switched on. For exam-
ple, if input R is hi, output RU is hi. At
the first rising edge of CLK out after
input R is brought low, the RU output
goes low. After exactly 8 more clock
periods the RL output goes high. This
injected delay is the deadtime.
This method of synchronizing is utilized
to guarantee that the deadtime is
always exactly the same (to the accu-
racy of the CLK frequency). This can be
very important in certain applications.
Unbalanced deadtime creates an offset
in the PWM output stage transfer func-
tion, and can cause saturation of the
induction machine control or the driven
transformer if not corrected within a few
cycles.
Fig. 1: Totem Pole configuration of
transistor switches; reason for dead-
time requirements
Deadtime in power circuits
Why is deadtime required?
Fig. 1 is typical of a switching power
conversion equipment output stage. It
has two (or typically more) switches. A
simple logic error - turning a transistor
on at the wrong instant - can cause
catastrophic failure in the right (or
wrong) circumstances.
In normal operation, when the state of
the output totem pole must change, the
conducting transistor is turned off.
Then, after a delay (usually called the
deadtime), the other transistor is turned
on. The delay is added to ensure that
there is no possibility of both transistors
conducting at the same time (this would
cause a short circuit of the DC link - a
"shoot through" - and would likely fail
both transistors in a few microseconds).
When the control logic commands a
switch to change to the off state,
several parasitics may delay/modify this
command. The propagation delay of
the control logic and gate drive buffer,
td (off) of the power transistor, storage
time (for bipolars) or tail time (for
IGBTs), voltage rise and current fall
times, etc., may be significant.
Problems Caused by Excessive
Deadtime
If a little is good, a lot should be better -
except with deadtime. Unfortunately,
deadband in the switching output stage
causes a nonlinearity in the power
circuit transfer function that may be
difficult for the control loop to remove.
Fig. 2 illustrates the problem. The
switching period T is:
T = t
1
+ t
2
+ DT
t
1
is the time Q1 is commanded on, t
2
is
the time Q2 is commanded on, and DT
is the deadtime. Assuming continuous
condition, and with current in the
direction of I
L1
:
t
hi
= t
1
+ DT
t
lo
= t
2
With current in the direction of I
L2
:
t
hi
= t
1
+ DT
t
lo
= t
2
+ DT.
The change in "apparent duty cycle" is
then twice the deadtime (2DT). If
deadtime is 5% of the cycle period, the
duty cycle, as load current crosses
zero, instantly changes by 10 %. This is
a significant nonlinearity that causes
zero crossing distortions in load current
and voltage that must be removed by
the feedback loop around the PWM
stage. If these nonlinearities get large
enough, the loop may not have the gain
or the speed to remove them. This