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Avoiding Instability In Rail-to-Rail CMOS Amplifiers Avoiding Instability In Rail-to-Rail CMOS Amplifiers
by Mike Wong, Director of Application Engineering,
Intersil Corporation
As the gate oxide thickness decreases in CMOS amplifiers, the maximum allowable
power supply voltage decreases. Channel length and width reductions enable the
development of high-frequency CMOS rail-to-rail I/O amplifiers that allow analog
circuits to operate at the same low supply voltage as their digital counterparts.
One potential drawback in these lower-power, smaller amplifier's feedback is amplifier
oscillation, which can occur when driving a capacitive load. This can happen when the
inductive output of the op amp, in conjunction with the capacitive load, creates an LC
resonant tank topology.
The capacitive load reactance -- in combination with the inductive drive impedance --
results in extra phase lag when the feedback is closed around the loop. A decreasing
phase margin introduces the possibility of amplifier oscillation when it can become very
hot and selfdestruct.
There are some well-known solutions to this challenge; the simplest is the addition of a
resistor in series with the output to force the feedback to come from the amplifiers direct
output while isolating the reactive load. The trade-off from this method is the sacrifice of
a small amount of the output voltage swing across the load.
Another straightforward solution is the application of a snubber network, which is a
resistor and capacitor placed in parallel with the capacitive load -- providing resistive
impedance across the load to diminish the output phase shift and so providing added
stability.
But there are other alternative solutions including three that can reduce amplifier
instability simply, and reliably.
These include:
1. Rreducing the feedback resistor value to minimize the impact of Cin
2. Introducing a Ccomp in parallel with RF
3. Engineering an increase of closed loop gain Fig. 1: Current Feedback Amplifier Simplified Schematic
The simplified schematic of a CMOS rail-to-rail I/O amplifier is shown in Fig. 1. It
consists of three stages:
Rail-to-rail input stage
Intermediate gain stage
Rail-to-rail output stage
The input is a differential voltage stage with differential current output. Its bandwidth
extends to over 320 MHz. The majority of the phase shift occurs over 100 MHz beyond
the bandwidth of the amplifier, which translates into a generous phase margin. The gate
capacitance of the differential input stage MOS transistors and package lead capacitance
combine for 2.5 pF of amplifier input capacitance, where the dominant pole of this
topology is set by internal compensation capacitors C1 and C2. This stage converts
differential current into differential voltage at the output; so we have differential voltage
input and a single-ended output.
To simplify analysis we assume that the input stage is a differential voltage buffer with
unity gain and also that the voltage gain of the stage is 50 dB, with the dominant pole
occurring at 11 kHz.
The output stage is a rail-to-rail topology using transistors connected in common-source
configuration. Unlike source-follower buffer output stages, the large gain of the common-
source output stage changes with the output-loading resistor while the bandwidth changes
with the output loading resistor and load capacitance. The complete amplifier open-loop frequency response (see Fig. 2) is a combination of
input, gain and output frequency responses. The 150 pF loading capacitance reduces the
bandwidth of the output stage resulting in an overall system bandwidth decrease and
phase margin reduction of 17°, a marginally-stable condition. When in unity gain
configuration, the buffer configuration with Vout and Vin- directly shorted, the amplifier
can drive a 150 pF and 200 load while remaining stable. The trouble occurs when a
resistor is placed in the feedback path.
Fig. 2: CMOS Rail-To-Rail Amplifier Open-Loop Response
The complete amplifier application circuit consists of the amplifier plus the feedback
resistor, RF, and the gain resistor, RG. If we select reasonable component values, such as
RF = 3 k and RG = 8.3 k, the feedback network combined with the 2.5 pF capacitor at
the negative input forms a low-pass network from the amplifier output to the negative
input. The frequency response of this feedback network shows a 45° phase shift at 30
MHz.
The feedback network reduces the overall system gain slightly because of the extra pole it
introduces. The most negative impact of this additional pole is that it reduces the phase
by a significant amount. Under a 150 pF and 200 loading condition, the system with an
RF = 3 k and RG = 8. 3 k feedback network, has a 11.5-MHz gain-bandwidth product
with 0° phase margin: and the system oscillates. Fig. 3: Loop Frequency Response w/ RF = 3 k and RG = 8.3 k
Solution 1:Reduce Feedback Resistor Value To Minimize The Impact Of Cin
The phase shift and loss of phase margin is caused by the RF/RG/Cin low-pass filter.
Reducing resistor values will shift the filter pole to a higher frequency (>30MHz). As RF
and RG are reduced to one-third the pole moves from 30MHz to around 90MHz. Fig. 4
shows the complete system frequency response. This is a very nice solution because the
GBW changes very little but phase margin improves significantly, to 14°, under the 200
and 150 pF condition. The system is now stable. The minor trade-off is that the
amplifier drives a lower feedback resistance slightly increasing power dissipation.
Fig. 4: Loop Frequency Response w/ Lower RF and RG Values Solution 2: Place Ccomp In Parallel With RF
This solution introduces a small compensation capacitor (Ccomp) in parallel with RF
without changing the values of RF or RG. The Ccomp capacitor introduces a phase lead
to cancel out the phase lag caused by Cin. The complete system frequency response with
a 5 pF Ccomp capacitor is shown in Fig. 5. The GBW changes very little but the phase
margin improves significantly: under 200 and 150 pF conditions, the phase margin
increases to 19°. The system is stable, while maintaining minimum power consumption.
Fig. 5: Complete Loop Frequency Response w/ 5 pF Ccomp
Solution 3: Increase Closed-Loop Gain
This solution uses a large RF and RG ratio to increase closed loop gain. We use 43 k
for RF and 8.3 k for RG in the example. The gain and phase curves of this RF and RG
combination show a pole at 9 MHz with 16 dB attenuation. The 16 dB attenuation
reduces the overall system gain by 16 dB. The complete system frequency response with
large closed-loop gain is in Fig. 6.
The overall system open-loop gain decreases by 16 dB, to 54 dB from 70 dB. As a result,
the GBW decreases to approximately 5 MHz. But, the phase margin improves
significantly. Under 200 and 150 pF load conditions, the phase margin increases to
20°. The system is now stabilized by sacrificing bandwidth. Fig. 6: Frequency Response w/ Large Closed-Loop Gain
Conclusions
Unlike traditional amplifiers, the common-source output stage of the rail-to-rail amplifier
has gain and bandwidth that is more sensitive to resistive / capacitive loading. The
bandwidth variation, along with the input capacitance, significantly impacts amplifier
stability.
These three possible solutions can reduce amplifier instability in most applications.
About The Author
Mike Wong is employed by Intersil Corporation at the Elantec Product Group where he is
Director of Application Engineering. He specializes in high-performance analog circuit
and power management applications. Previously Mike worked at ASTEC;.he earned a
BSEE from The University of California at Davis. Contact:
mwong@intersil.com