rs for Advanced Computer Systems (HIP6500BEVAL1, HIP6502BEVAL1) 1
TM
AN9862.1
ACPI Controllers for Advanced Computer
Systems (HIP6500BEVAL1, HIP6502BEVAL1)
Introduction
The Advanced Conguration and Power Interface
specication (ACPI; [1]), written by a consortium
representing Intel, Microsoft and Toshiba, attempts to evolve
the current collection of power management methods and
conguration interfaces into a well-specied and unied
power management and conguration mechanism. The key
objective in the ACPI specication is to transfer all control of
power management and conguration functions to the
operating system, thus enabling Operating System Directed
Power Management (OSPM). ACPI-compliant systems will
benet from a robust interface for conguring motherboard
devices, a versatile power management interface enabling a
wide variety of solutions with full operating-system support,
and not lastly, a realm of new, intelligent possibilities added
to the already broad span of PC uses.
The HIP6500B/02B ICs are to be used in conjunction with a
second integrated circuit to provide a complete ACPI-
sanctioned motherboard power regulation solution. The
HIP6500B/HIP6020 and HIP6502B/HIP6020 chip sets
(HIP6021 can substitute HIP6020 in either chip set) produce
the processor core, GTL bus, memory controller hub, and
AGP 4x voltages, as well as the 3.3V standby, 2.5V clock,
SDRAM/RDRAM memory (or both, simultaneously), 3.3V
and 5V dual voltage planes necessary for a complete PIII-
Camino (or equivalent) system implementation. [2, 3, 5, 6]
Quick Start Evaluation
Important!
Given the specialized nature of the HIP6500B and
HIP6502B, the HIP6500B/02BEVAL1 boards are meant to
be evaluated only with an ATX power supply. Furthermore,
only an ACPI-ready ATX supply can be used to power-up the
evaluation boards (720mA capability on 5VSB output; ATX
Specication v2.02, [4]). Standard laboratory power supplies
are not suitable for powering up this evaluation board.
Circuit Setup Set Up JP1, JP2, and JP2, JP3
Before connecting the input ATX supply to the
HIP6500B/02BEVAL1 board, consult the circuit schematic
and data sheets and set the JP1 and JP2 conguration
jumpers on the HIP6500BEVAL1, and JP2 and JP3 jumpers
on the HIP6502BEVAL1 according to the conguration you
wish to emulate. These particular congurations are latched
in during certain times, but can be subsequently changed at
certain times. See HIP6500B/02B data sheets for
information on the available congurations and how to set
them. Connect the Input Power Supply
Ensuring that the supply is not plugged into the mains, or
that the AC switch is off (if provided), connect the main ATX
output connector to J1. Connect the Output Loads
Connect typical standby loads to all the evaluation boards
outputs. Consult Table 1 for maximum loads supported by
the design of the HIP6500B/02BEVAL1 in the conguration
received; consult the HIP6500B/02BEVAL1 Modications
chapter for information on modifying the evaluation board to
meet your special needs. Set Start-Up State (Active Is Recommended)
If start-up in active state (S0/S1/S2) is desired, ensure both
S3 (SW2) and S5 (SW3) switches are in the off position
(away from S3 or S5 marking). Ensure the ATX ON switch
is also in the off position.
Set either the S3 or the S5 standby switch for start-up in
either of the standby states. IMPORTANT: only one switch
needs to be actuated, so select the standby state by turning
on the switch with that name - the signal conditioning
circuitry ensures correct S3 and S5 pin stimulation.
Operation Provide Bias Voltage to the Board
Plug the ATX supply into the mains. If the supply has an AC
switch, turn it on. The 5VSB (LP4) LED should light up,
indicating the presence of 5V standby voltage on board. Examine Start-Up Waveforms
Sleep state start-up is immediate following application of
bias voltage. Using an oscilloscope or other laboratory
equipment, you may study the ramp-up and/or regulation of
the controlled voltages, according to the specic JP1/JP2, or
JP2/JP3 conguration previously set and the specic
standby state selected.
For start-up into an active state (standby switches set off
prior to application of bias voltage), ip on the ATX ON
switch (SW1). This will turn on the main ATX outputs and the
HIP6500B/02B will start up into active state. Once turned on,
SW1 needs not be turned off until bias is removed from the
board. Examine Output Quality Under Varying Loads
In either state (sleep or active) vary the output loads to
simulate computer loads typical of the specic operating
state the circuit is in.
Application Note
July 2000
Author: Bogdan M. Duduman
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil Corporation 2000 2 Examine State Transitions
For subsequent transitions into standby states, leave the
main ATX outputs enabled (SW1 on); the circuit will
automatically turn them off when entering a standby state.
To enter a standby state, turn on the respective switch. The
S3 LED will light up to indicate S3 standby state, while S5
state will illuminate both S3 and S5 LEDs. However, the
HIP6500B/02B will ignore any illegal transition requests,
such as from S3 state to S5 state or vice versa, as shown in
Figure 1.
Fault Handling
In case of a fault condition (input or output under-voltage -
such as a suddenly shorted output or a loss of an input
power rail), the FAULT pin asserts a logic high, shutting
down the ATX supplys main outputs. To recover from such a
shutdown, press the SHUTDOWN/CLEAR FAULT button
(PB1). Depressing PB1 will reset the IC and initiate a soft-
start sequence, thus clearing the FAULT, and enabling the
main ATX outputs.
If jumper JP3/1(respectively, JP3 on the 6500 and JP1 on
the 6502 evaluation board) FAULT LATCH is removed, the
FAULT output will not latch the circuit. The circuit appears to
latch off because the FAULT signal shuts down the ATX
supply, cutting off the input supply to the faulting output, and
thus keeping it from ever recovering from the fault condition.
However, it is not recommended to test the circuit against
output under-voltages (output short-circuits) with the fault
latch jumper removed. Due to the very slow response of the
ATX supply in response to a shutdown request, the external
N/P-MOS switches (Q4, Q5, Q6, and Q7) in use at the time
of testing could fail as a result of sustained over-current
through the drain-source junction and bond wires. The
FAULT latch circuit acts on the SS pin directly, shutting down
the IC quickly. To protect the external switches it is strongly
recommended that JP3/1 FAULT LATCH jumper is shunted
throughout the operation of the board.
Conguring Sleep State Support
Sleep state support on the 3.3V
DUAL
and 5V
DUAL
outputs of
the HIP6500BEVAL1 are user-congurable through jumpers
JP1 and JP2. Sleep state support on the 2.5V
MEM
,
3.3V
MEM
, and 5V
DUAL
outputs of the HIP6502BEVAL1 are
user-congurable through jumpers JP2 and JP3 (consult
data sheets for sleep support details). The congurations
can be changed prior to 5VSB application, during active
state operation (additionally, during S4/S5 operation for
HIP6502Bs memory selection), as well as during chip
shutdown (PB1 pressed). During all other times, the
congurations are internally latched and any changes in the
MSEL, EN3VDL and EN5VDL pins logic status are ignored.
HIP6500B/02BEVAL1 Reference Design
General
Both evaluation boards are built on 2-ounce, 4-layer, printed
circuit board (see last six pages of this application note for
layout plots). Most of the components specic to the
evaluation board alone, which are not needed in a real
computer application, are placed on the bottom side of the
board. Assuming the input supplies and the controlled output
planes have their own on-board ltering (capacitors), the
only components required to implement this ACPI 5-voltage
controller/regulator solution are contained within the white
rectangle surrounding the HIP6500B/02B on the top side of
the board. All the additional circuitry contained on board has
the role of duplicating the computer environment the chip
would operate in. Since this additional circuitry would clutter
and detract from the readability of the schematic, most of it
was grouped in two blocks, named SIGNAL
CONDITIONING and FAULT LATCH (see evaluation board
schematics).
The boards also contain a serpentine resistor which
occupies about 1/3 of both top and bottom sides of the
board. The ATX supply requires some minimum loading on
the +5V output in order to stay active; lack of this minimum
loading causes the ATX to shut down all its outputs, except
+5VSB. This minimum load is specied as 1A, but most
supplies will stay active with as little as 400-500mA. The
embedded resistor is designed to draw a current of about 1A
(typical). If the current draw is insufcient to keep the power
supply active, try reducing the value of the embedded
resistor. Shorting out the W1 footprint, on the back side of
the board, effectively shorts out 1/4 of the resistive trace,
increasing the current draw by 30%. Similarly, shorting out
W2 reduces the trace by 50%, thus doubling the current
draw from the +5V output. If either W1 or W2 are shorted, it
is advised that active state operation time be reduced as to
avoid severe overheating of the board (in case the 5V
FIGURE 1. HIP6500B/02B LEGAL/ILLEGAL STATE
TRANSI