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How to connect a small page NAND Flash memory to STR710 March 2006
Rev 1
1/17
AN2287
Application note
How to connect a small page NAND Flash memory to STR710
Introduction
This document describes the hardware and software necessary to drive an
STMicroelectronics Small Page NAND Flash Memory by an STR710. Small Page NAND
Flash is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND
technology. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V
supply. The size of a Page is 528 Bytes (512 + 16 spare) with a x8 bus width.
The devices covered by this Application Note are: NAND128W3A NAND256W3A NAND512W3A NAND01GW3A
Small Page NAND Flash devices are connected using STR710 External Memory Interface
(EMI) without gluelogic.
www.st.com Contents
AN2287
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Contents
1
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
NAND basic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
NAND functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AN2287
Signal descriptions
3/17
1 Signal
descriptions
The following tables summarize the signals used in this application note.
Table 1
describes
all the Small Page NAND Flash signals.

Table 1.
Small Page NAND Flash Signal Descriptions
Signal
Signal Name
Description
I/O0-I/O7
Data
Input/Outputs
Input/Outputs 0 to 7 are used to input the selected address, output
the data during a Read operation or input a command or data
during a Write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is
deselected or the outputs are disabled.
ALE
Address Latch
Enable
The Address Latch Enable activates the latching of the Address
inputs in the Command Interface. When ALE is high, the inputs are
latched on the rising edge of Write Enable.
CLE
Command
Latch Enable
The Command Latch Enable activates the latching of the
Command inputs in the Command Interface. When CLE is high,
the inputs are latched on the rising edge of Write Enable.
CE
Chip Enable
The Chip Enable input activates the memory control logic, input
buffers, decoders and read circuitry. When Chip Enable is low
(VIL) the device is selected. If Chip Enable goes High (VIH) while
the device is busy, the device remains selected and does not go
into standby mode.
RE
Read Enable
The Read Enable, RE, controls the sequential data output during
Read operations. Data is valid tRLQV after the falling edge of RE.
The falling edge of RE also increments the internal column
address counter by one.
WE
Write Enable
The Write Enable input, WE, controls writing to the Command
Interface, Input Address and Data latches. Both addresses and
data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10µs (min) is
required before the Command Interface is ready to accept a
command. It is recommended to keep Write Enable high during
the recovery time.
WP
Write Protect
The Write Protect pin is an input that gives a hardware protection
against unwanted program or erase operations. When Write
Protect is Low, VIL, the device does not accept any program or
erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during
power-up and power-down.
RB
Ready/Busy
The Ready/Busy output, RB, is an open-drain output that can be
used to identify if the P/E/R Controller is currently active.
When Ready/Busy is Low (VOL) a read, program or erase
operation is in progress. When the operation completes
Ready/Busy goes High (VOH). The use of an open-drain output
allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that
one, or more, of the memories is busy. Memory array organization
AN2287
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2
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The Small Page NAND Flash devices described in this application note have a x8 bus width.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification. So each pages are split into a main area with two half pages
of 256 Bytes each and a spare area of 16 Bytes.
Figure 1.
Small Page NAND Flash memory array blocks
x8 DEVICES
Block=32 Pages
Page=528 Bytes (512+16)
512 Bytes
16
Bytes
8 bits
Spare
Area
2nd half Page
(256 bytes)
1st half Page
(256 bytes)
Page Buffer, 512 Bytes
8 bits
Block
Page
512 Bytes
Bytes
16
Table 2.
NAND Size
Num Blocks
NAND128W3A
1024 blocks
NAND256W3A
2048 blocks
NAND512W3A
4096 blocks
NAND01GW3A
8192 blocks AN2287
Hardware interface
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3 Hardware
interface
The Small Page NAND Flash NANDxxx3WA is connected with STR710 using an External
Memory Interface (EMI) bus, without glue logic.
Figure 2.
NANDxxx3WA signal mapping with STR710
In this application note, NAND Flash Memory is mapped on EMI bank3, so Memory Chip
Enable is connected with CS.3 STR71x signal memory and I/O0..I/O7 are connected with
D0..D7 microcontroller EMI bus data signals. Memory control signals are connected with
A23..A20 EMI bus address signals. Refer to the table below for further details:

Table 3.
NAND Flash and STR710 EMI Bus signal connections
NAND Flash signals
STR710 EMI Bus signals
I/0 0..7
D0..D7
RE
nRD
CE
CS.3 (GPIO 2.3)
CLE
A21 (GPIO 2.5)
ALE
A22(GPIO 2.6)
WE
nWE0
WP
A20 (GPIO 2.7)
RB
A23 (GPIO 2.4)
A23
D0
D1
D2
D3
D4
D5
D6
D7
nRD
CS.3
A21
A22
nWE0
A20
8
9
16
17
18
19
12
37
13
36
6
7
29
30
31
32
41
42
43
44
RE
CE
CLE
ALE
WE
WP
V
CC
V
CC
V
SS
V
SS
GND
R/B
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NANDxxxW3A
NA
ND FLASH Firmware
AN2287
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4 Firmware
The Software library is organized in two files, Nand_flash.h and Nand_flash.c
In the header file, nand_flash.h, there are device definitions, type definitions and function
prototypes. In the file nand_flash.c, all the functions to use the NAND flash device are
implemented.
The firmware is developed in two layers, one low-level driver to implement basic NAND
Flash functions and a medium-level driver to implement NAND Flash complex functions.
The firmware also includes a module to configure GPIO and EMI from the STR710 standard
software library.
Figure 3.
Software library interaction with the firmware layers
4.1
NAND basic functions
There are five standard basic operations controlling the memory:
Command Input : NandCommand(Command Type)
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable Is High. All bus write operations to the device are interpreted by the
Memory Command Interface. The Commands are input on I/O0-I/O7 and are latched on the
rising edge of Write Enable when the Command Latch Enable signal is high. Device
operations are selected by writing specific commands to the Command Register. The two-
step command sequences for program and erase operations are imposed to maximize data
security.
The Command Registers are summarized in the following table.
Application Layer
Medium-level NAND driver
Low-level NAND driver
STR710 software library
(emi.c gpio.c) AN2287
Firmware
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Command Types are defined inside the file nand_flash.h
#define Nand_AreaA
0x00
#define Nand_AreaB
0x01
#define Nand_AreaC
0x50
#define Nand_ReadStatusReg
0x70
#define Nand_PageProgram
0x80
#define Nand_EndPageProg
0x10
#define Nand_ReadElectSign
0x90
#define Nand_BlockErase
0x60
#define Nand_ConfirmErase
0xD0
#define Nand_Reset
0xFF
#define Nand_CopyBack
0x8A
Command La