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Low-swing on-chip signaling techniques: effectiveness and robustness - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 264
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 3, JUNE 2000
Low-Swing On-Chip Signaling Techniques:
Effectiveness and Robustness
Hui Zhang, Student Member, IEEE, Varghese George, Student Member, IEEE, and Jan M. Rabaey, Fellow, IEEE
AbstractThis paper reviews a number of low-swing on-chip in-
terconnect schemes and presents a thorough analysis of their effec-
tiveness and limitations, especially on energy efficiency and signal
integrity. In addition, several new interface circuits presenting even
more energy savings and better reliability are proposed. Some of
these circuits not only reduce the interconnect swing, but also use
very low supply voltages so as to obtain quadratic energy savings.
The performance of each of the presented circuits is thoroughly
examined using simulation on a benchmark interconnect circuit.
Significant energy savings up to a factor of six have been observed.
Index TermsDigital CMOS, low-power design, low-voltage,
performance tradeoffs, reliability, special low-power 99.
I. I
NTRODUCTION
I
N THE deep-submicron era, interconnect wires (and the as-
sociated driver and receiver circuits) are responsible for an
ever increasing fraction of the energy consumption of an inte-
grated circuit. Most of this increase is due to global wires, such
as busses, clock, and timing signals. For gate array and cell-li-
brary-based designs, D. Liu et al. [1] found that the power con-
sumption of wires and clock signals can be up to 40% and 50%
of the total on-chip power consumption, respectively. The im-
pact of interconnect is even more significant for reconfigurable
circuits. Measured over a wide range of applications, more than
90% of the power dissipation of traditional FPGA devices have
been reported to be due to the interconnect [2].
Obviously, techniques that can help to reduce these ratios are
desirable. For chip-to-chip interconnects, wires are treated as
transmission lines, and many low-power I/O schemes were pro-
posed at both circuit level (e.g., GTL transceiver [3]) and coding
level (e.g., work-zone encoding [4] and bus-invert coding [5]).
In this paper, the main focus is how to reduce the power con-
sumption of on-chip interconnects. Short of reducing the av-
erage length of the wires and their fanout by using advanced pro-
cesses or improved architectures, reducing the voltage swing of
the signal on the wire is one of the best solutions toward getting
better energy efficiency. First, we will analyze the effectiveness
of a number of reduced-swing interconnect schemes that have
been proposed in the literature [6][11]. In addition, a number
of novel or modified circuits will be introduced, simulated, and
critiqued. To present a fair and realistic base for comparison,
a single test circuit will be used. Overall, it is found that the
proposed schemes present a wide range of potential energy re-
Manuscript received February 18, 1999; revised August 31, 1999. This work
was supported by DARPA under the ACS PLEIADES project.
The authors are with the Berkeley Wireless Research Center, EECS
Department, University of California, Berkeley, CA 94704 USA (e-mail:
hui@eecs.berkeley.edu).
Publisher Item Identifier S 1063-8210(00)04349-3.
Fig. 1.
(a) Benchmark test architecture. (b) Interconnect model.
ductions, yet that other considerations such as complexity, reli-
ability, and performance play an important role as well. We will
therefore pay special attention to each of these factors in our
analysis.
The paper is organized as follows. First, the benchmark ex-
ample and the set of quality metrics that will be used in all
simulations and comparisons are presented. What follows are
a review and comparison of a number of architectures, obtained
from the open literature. Several novel or improved low-swing
schemes are proposed and analyzed in Section III. Finally, Sec-
tion IV brings them all together and draws some conclusions. At
the end of the paper, an Appendix is attached to provide detailed
descriptions for the physical models of important noise sources.
II. T
EST
A
RCHITECTURE AND
Q
UALITY
M
ETRICS
Presenting a fair comparison for the various interconnect
schemes that are presented in this paper requires a common and
fair testbed. Fig. 1(a) illustrates the schematic of our benchmark
interconnect circuit. The driver converts a full-swing input into
a reduced-swing interconnect signal, which is converted back
to a full-swing output by the receiver. The interconnect line
is a metal-3 layer wire with a length of 10 mm, modeled by
a
distributed RC model with an extra capacitive load
distributed along the wire (for fanout), as shown in Fig. 1(b).
To fairly compare the delays of the different schemes, we
deliberately add an inverter prior to the driver and an inverter
after the receiver with 20-fF capacitive load. Both inverters
are sized with
m and
m. All circuit
comparisons are based on the MOSIS HP complementary
metaloxidesemiconductor (CMOS) 14TB process parame-
ters and spice models. The minimum drawn channel length for
this process is set to 0.6
m with an effective channel length
of 0.5
m.
For each of the circuits under test, we consider the following
metrics.
10638210/00$10.00 © 2000 IEEE ZHANG et al.: LOW-SWING ON-CHIP SIGNALING TECHNIQUES: EFFECTIVENESS AND ROBUSTNESS
265
TABLE I
T
YPICAL
N
OISE
S
OURCES
Energy: The dynamic switching energy of the wire for a
full switching is given by (1). When comparing schemes
with different types of circuit design such as dynamic de-
sign versus static design, differences in data activity are
taken into account. The short-circuit current and leakage
current are relatively less important compared to the dom-
inant switching energy, but will be also under considera-
tion. The total energy shall include the contributions from
both the driver and receiver
driver
(1)
Design complexity.
Delay.
Reliability: Three main sources of reliability degradation
are considered: process variation, voltage supply noise,
and interline crosstalk.
We use the worst case noise analysis method presented in [12]
to measure the reliability of each circuit. The noise sources are
classified into two categories: the proportional noise sources and
the independent noise sources
(2)
represents those noise sources that are proportional
to the magnitude of signal swing
, such as crosstalk,
and signal-induced power supply noise.
includes those
noise sources that are independent of
such as receiver
input offset (due to process variation), receiver sensitivity, and
signal-unrelated power supply noise. Table I summarizes the
noise sources and their contributions, and detailed descriptions
are provided in Section VI (Appendix).
The cross-talk coupling coefficient
is derived from the
ratio between coupling capacitance and wire load capacitance.
The cross-talk noise attenuation for the static driver scenario is
achieved by increasing the timing budget for the signal so that
the charge loss due to the cross-talk noise can be recovered by
the driver. The signal-induced supply noise is estimated to be
5% and 1% of the signal swing for single-ended and differential
signaling, respectively. The receiver input offset and sensitivity
are dependent on the receiver circuits in question, and will be
Fig. 2.
Conventional level converter.
individually assessed for each scheme (e.g., for the CMOS in-
verter, its input offset and sensitivity are around 150 mV, respec-
tively). The signal-unrelated power supply noise is assumed to
be 5% of the magnitude of power supply for a well-designed
power distribution network.
The power-supply attenuation coefficient is defined as the
change of the switching threshold voltage induced by an unit
change of the supply voltage. The transmitter offset results from
the parameter mismatch between the transmitter and receiver,
such as threshold voltage mismatch and reference voltage vari-
ation.
We use the worst case signal-to-noise ratio (SNR) defined
in (3) as a measure of the reliability of each circuit. The noise
margin is defined as (SNR 1)
SNR
(3)
III. R
EVIEW OF
E
XISTING
L
OW
-S
WING
I
NTERFACE
C
IRCUITS
In this section, seven low-swing circuit schemes (three static
and four dynamic) are reviewed, and the pros and cons of each
approach are enumerated. The important design metrics of the
circuits are compared based on simulation results.
A. Static Driver with Reduced Supply
The conventional level converter (CLC) shown in Fig. 2 rep-
resents the traditional way of converting a low-swing signal
back to a full swing one. The driver uses an extra low-voltage
supply to drive the interconnect from zero to VDD . Although
the noise margin is reduced, this circuit is very robust against
noise, as the receiver behaves as a differential amplifier, and
the internal inverter further attenuates some noise through re-
generation. The symmetric driver and level converter (SDLC),
proposed in [7], also falls in the same category. It requires two
extra power rails to limit the interconnect swing and uses spe-
cial low-
devices ( 0.1 V) to compensate for the current-drive
los