DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 Quad, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
FEATURES
· · · · · · · · · · · · · · · · · Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA Full-Scale Current with VREF = ±10 V 0.5-µs Settling Time Midscale or Zero-Scale Reset Four Separate 4Q Multiplying Reference Inputs Reference Bandwidth: 10 MHz Reference Dynamics: -105 dB THD SPITM-Compatible 3-Wire Interface: 50-MHz Double Buffered Registers Enable Simultaneous Multichannel Update Internal Power-On Reset Compact SSOP-28 Package Industry-Standard Pin Configuration DESCRIPTION
The DAC8803 is a quad, 14-bit, current-output digital-to-analog converter (DAC) designed to operate from a single +2.7-V to 5-V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A doubled buffered serial data interface offers high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip select (CS). In addition, a serial data out pin (SDO) allows for daisy chaining when multiple packages are used. A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turn on. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1. The DAC8803 is packaged in an SSOP package. APPLICATIONS
Automatic Test Equipment Instrumentation Digitally-Controlled Calibration VREFA B C D D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 RFBA Input Register R DAC A Register R DAC A IOUTA AGNDA RFBB 14 Input Register R DAC B Register R DAC B IOUTC AGNDB RFBC Input Register R DAC C Register R DAC C IOUTC AGNDC SDO SDI CLK CS EN DAC A B C D 2:4 Decode Input Register R DAC D Register R DAC D RFBD IOUTD AGNDD Power-On Reset AGNDF DGND RS MSB LDAC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005­2006, Texas Instruments Incorporated DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1)
MINIMUM RELATIVE ACCURACY (LSB) ±1 DIFFERENTIAL NONLINEARITY (LSB) ±1 SPECIFIED TEMPERATURE RANGE -40°C to +85°C PACKAGELEAD SSOP-28 PACKAGE DESIGNATOR DB ORDERING NUMBER DAC8803IDBT DAC8803IDBR TRANSPORT MEDIA QUANTITY Tape and Reel, 250 Tape and Reel, 2500 PRODUCT DAC8803 (1) For the most current specifications and package information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com ABSOLUTE MAXIMUM RATINGS (1)
DAC8803 VDD to GND VREF to GND Logic inputs and output to GND V(IOUT) to GND AGNDX to DGND Input current to any pin except supplies Package power dissipation Thermal resistance, JA 28-Lead shrink surface-mount (RS-28) Maximum junction temperature (TJmax) Operating temperature range, Model A Storage temperature range (1) -0.3 to +8 -18 to +18 -0.3 to +8 -0.3 to VDD + 0.3 -0.3 to +0.3 ±50 (TJmax - TA)/JA 100 150 -40 to +85 -65 to +150 UNIT V V V V V mA W °C/W °C °C °C Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted.
DAC8803 PARAMETER STATIC PERFORMANCE (1) Resolution Relative accuracy Differential nonlinearity Output leakage current Full-scale gain error Full-scale tempco (2) Feedback resistor REFERENCE INPUT VREFX Range Input resistance Input resistance match Input capacitance (2) ANALOG OUTPUT Output current Output capacitance (2) LOGIC INPUTS AND OUTPUT Input low voltage Input high voltage Input leakage current Input capacitance (2) Logic output low voltage Logic output high voltage INTERFACE TIMING (2), (3) Clock width high Clock width low CS to Clock setup Clock to CS hold Clock to SDO prop delay Load DAC pulsewidth Data setup Data hold Load setup Load hold (1) (2) (3) tCH tCL tCSS tCSH tPD tLDAC tDS tDH tLDS tLDH 25 25 0 25 2 25 20 20 5 25 20 ns ns ns ns ns ns ns ns ns ns VIL VIL VIH VIH IIL CIL VOL VOH IOL = 1.6 mA IOH = 100 µA 4 VDD = +2.7 V VDD = +5 V VDD = +2.7 V VDD = +5 V 2.1 2.4 1 10 0.4 0.6 0.8 V V V V µA pF V V IOUTX COUTX Data = 3FFFh Code-dependent 1.6 50 2.5 mA pF VREFX RREFX RREFX CREFX Channel-to-channel -15 4 5 1 5 15 6 V k % pF DNL IOUTX IOUTX GFSE TCVFS RFBX VDD = 5 V Data = 0000h, TA = 25°C Data = 0000h, TA = TA max Data = 3FFFh ±0.75 1 14 ±1 ±1 10 20 ±3 Bits LSB LSB nA nA mV ppm/°C k SYMBOL CONDITIONS MIN TYP MAX UNIT All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8803 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C. These parameters are specified by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Submit Documentation Feedback 3 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless otherwise noted.
DAC8803 PARAMETER SUPPLY CHARACTERISTICS Power supply range Positive supply current VDD
RANGE SYMBOL CONDITIONS MIN 2.7 TYP MAX 5.5 UNIT V µA µA mW % IDD IDD Logic inputs = 0 V, VDD = +4.5 V to +5.5 V Logic inputs = 0 V, VDD = +2.7 V to +3.6 V Logic inputs = 0 V VDD = ±5% To ±0.1% of full-scale, Data = 0000h to 3FFFh to 0000h To ±0.006% of full-scale, Data = 0000h to 3FFFh to 0000h VREFX = 100 mVRMS, Data = 3FFFh, CFB = 3 pF VREFX = 10 V, Data = 1FFFh to 2000h to 1FFFh Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz Data = 0000h, VREFB = 100 mVRMS, Adjacent channel, f = 100 kHz CS = 1 and fCLK = 1 MHz VREF = 5 VPP, Data = 3FFFh, f = 1 kHz f = 1 kHz, BW = 1 Hz 2 1 5 2.5 0.025 0.006 Power dissipation Power supply sensitivity AC CHARACTERISTICS (4) Output voltage settling time PDISS PSS ts ts 0.3 0.5 10 1 -70 -100 1 -105 12 µs µs MHz nV/s dB dB nV/s dB nV/Hz Reference multiplying BW DAC glitch impulse Feedthrough error Crosstalk error Digital feedthrough Total harmonic distortion Output spot noise voltage (4) BW -3 dB Q VOUTX/VREFX VOUTA/VREFB Q THD en All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier. 4 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 PIN CONFIGURATIONS
DAC8803 (TOP VIEW) AGNDA IOUTA VREFA RFBA MSB RS VDD CS CLK SDI RFBB VREFB IOUTB AGNDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AGNDD IOUTD VREFD RFBD DGND VSS(1) AGNDF LDAC SDO (1) NC RFBC VREFC IOUTC AGNDC Note (1): No internal connection PIN DESCRIPTION
PIN 1, 14, 15, 28 2, 13, 16, 27 3, 12, 17, 26 4, 11, 18, 25 5 6 7 8 9 10 19 20 21 22 23 24 NAME AGNDA, AGNDB, AGNDC, AGNDD IOUTA, IOUTB, IOUTC, IOUTD VREFA, VREFB, VREFC, VREFD RFBA, RFBB, RFBC, RFBD, MSB RS VDD CS CLK SDI NC SDO LDAC AGNDF VSS DGND DAC A, B, C, D Analog ground DAC A, B, C, D Current output DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale output voltage. Can be tied to VDD. Establish voltage output for DAC A, B, C, D by connecting to external amplifier output. MSB Bit set during a reset pulse (RS) or at system power-on if tied to ground or VDD. Reset pin, active low. Input register and DAC registers are set to all zeros or half-scale code (2000h) determined by the voltage on the MSB pin. Register data = 2000h when MSB = 1. Positive power-supply input. Specified range of operation +2.7 V to +5.5 V. Chip select; active low input. Disables shift register loading when high. Transfers shift register data to input register when CS/LDAC goes high. Does not affect LDAC operation. Clock input; positive edge triggered clocks data into shift register Serial data input; data loads directly into the shift register. Not connected; leave floating Serial data output; input data load directly into shift register. Data appears at SDO, 17 clock pulses after input at the SDI pin. Load DAC register strobe; level sensitive active low. Transfers all input register data to the DAC registers. Asynchronous active low input. See Table 1 for operation. High current analog force ground. No internal connection. Digital ground. DESCRIPTION Submit Documentation Feedback 5 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted. Channel A
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 1. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_ C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 2. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 3. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 4. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 5. Figure 6. 6 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted. Channel B
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 7. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_ C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 8. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 9. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 10. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 11. Figure 12. Submit Documentation Feedback 7 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted. Channel C
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 13. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 14. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 15. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 16. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 17. Figure 18. 8 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted. Channel D
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 19. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_ C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 20. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 21. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DNL (LSB) TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 22. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 23. Figure 24. Submit Documentation Feedback 9 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
180 160 Supply Current, IDD (µA) 140 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Logic Input Voltage (V) VDD = +2.7V VDD = +5.0V
6 0 -6 - 12 - 18 - 24 - 30 - 36 - 42 - 48 - 54 - 60 - 66 - 72 - 78 - 84 - 90 - 96 - 102 - 108 - 114 1 0 REFERENCE MULTIPLYING BANDWIDTH
0x3FFF 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0x0000 A ttenu ation (dB) 1 00 1k 10k 10 0k 1M 10M 100 M B and w idth (H z) Figure 25. DAC GLITCH Figure 26. DAC SETTLING TIME Output Voltage (50mV/div) Code: 1FFFh to 2000h Output Voltage (5V/div) Voltage Output Settling LDAC Pulse Trigger Pulse Time (0.2µs/div) Time (0.1µs/div) Figure 27. IDD vs TEMPERATURE
5.0 4.5 4.0 3.5 IDD (µA) 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 2.7V 5.0V Endpoint Error (mV) 2 DAC C 1 0 3 Figure 28. ENDPOINT ERROR vs TEMPERATURE DAC B DAC A -1 -2 -3 DAC D 40 60 80 100 -40 -20 0 Temperature (_C) 20 40 Temperature (_ C) 60 80 100 Figure 29. Figure 30. 10 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel A
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 31. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_ C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 32. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 33. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 34. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 35. Figure 36. Submit Documentation Feedback 11 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel B
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 37. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 38. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 39. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 40. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 41. Figure 42. 12 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel C
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 43. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = -40_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 44. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 45. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 46. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 47. Figure 48. Submit Documentation Feedback 13 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. Channel D
LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +25_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +25_C Figure 49. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code DNL (LSB) TA = -40_ C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 50. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = -40_ C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 51. LINEARITY ERROR vs DIGITAL INPUT CODE
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Digital Input Code TA = +85_C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 Figure 52. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
TA = +85_C 6144 8192 10240 12288 14336 16383 Digital Input Code Figure 53. Figure 54. 14 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
DAC GLITCH
3 Output Voltage (50mV/div) 2 Endpoint Error (mV) DAC C 1 0 DAC A -1 -2 -3 Time (0.2µs/div) -40 -20 0 20 40 Temperature (_ C) 60 80 100 DAC D DAC B ENDPOINT ERROR vs TEMPERATURE Code: 1FFFh to 2000h LDAC Pulse Figure 55. Figure 56. TIMING INFORMATION
SDI A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D1 D0
Input REG. LD CLK tCSS
CS tds tdh tch tcl tcsh tlds LDAC tpd
SDO tLDH tLDAC Figure 57. DAC8803 Timing Diagram Submit Documentation Feedback 15 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 THEORY OF OPERATION CIRCUIT OPERATION
The DAC8803 contains four, 14-bit, current-output, digital-to-analog converters (DACs) respectively. Each DAC has its own independent multiplying reference input. The DAC8803 uses a 3-wire SPI-compatible serial data interface, with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage changes. D/A Converter The DAC8803 contains four current-steering R-2R ladder DACs. Figure 58 shows a typical equivalent DAC. Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full 14-bit accuracy. The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the internal 5 k feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D) according to Equation 1: D V OUT + *VREF 16384 (1) Note that the output polarity is opposite to the VREF polarity for dc reference voltages.
R VREFX 2R 2R 2R R 5 kW R R VDD RFBX S2 S1 IOUTX AGNDF AGNDX From other DACs AGND DGND Digital interface connections omitted for clarity. Switches S1 and S2 are closed. VDD must be powered. Figure 58. Typical Equivalent DAC Channel The DAC is also designed to accommodate ac reference input signals. The DAC8803 accommodates input reference voltages in the range of -15 V to +15 V. The reference voltage inputs exhibit a constant nominal input resistance of 5 k, ±20%. On the other hand, the DAC outputs IOUTA, B, C, D are code-dependent and produce various output resistances and capacitances. The choice of external amplifier should take into account the variation in impedance generated by the DAC8803 on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor (CFB) may be needed to provide a critically damped output response for step changes in reference input voltages. 16 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 Figure 26 shows the gain versus frequency performance at various attenuation settings using a 3 pF external feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions, clean power supply with low ripple voltage capability should be used. Switching power supplies are usually not suitable for this application because of the higher ripple voltage and PSS frequency-dependent characteristics. It is best to derive the DAC8803 5-V supply from the system analog supply voltages. (Do not use the digital 5-V supply.) See Figure 59.
15 V 2R 5V R VDD R VREFX 2R 2R 2R R 5 kW 15 V S2 S1 IOUTX AGNDF AGNDX From other DACs AGND A1 VEE Load DGND Digital interface connections omitted for clarity. Switches S1 and S2 are closed. VDD must be powered. VCC VOUT R R Analog Power Supply RFBX Figure 59. Recommended Kelvin-Sensed Hookup Submit Documentation Feedback 17 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 VREF A B C D CS EN CLK SDI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A0 A1 14 VDD RFBA DAC A IOUTA AGNDA Input Register R DAC A Register R Input Register R DAC B Register R RFBB DAC B IOUTC AGNDB SDO DAC A B C D 2:4 Decode
Input Register R DAC C Register R RFBC DAC C IOUTC AGNDC RFBD
Input Register R DAC D Register R DAC D IOUTD AGNDD Set MSB PowerOn Reset Set MSB AGNDF DGND MSB LDAC RS Figure 60. System Level Digital Interfacing SERIAL DATA INTERFACE
The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8803 is clocked into the serial input register in a 16-bit data-word format. MSB bits are loaded first. Table 2 defines the 16 data-word bits for the DAC8803. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state. Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the DAC8803. Keeping the CS line low between the first and second byte transfers results in a successful serial register update. 18 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8803, Table 2 and Table 3 define the characteristics of the software serial interface. Figure 61 shows the equivalent logic interface for the key digital control pins for the DAC8803.
To Input Register CS Address Decoder A B C D CLK SDI EN Shift Register SDO 17th Clock Figure 61. DAC8803 Equivalent Logic Interface Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1). POWER ON RESET
When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place. ESD Protection Circuits All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD as shown in Figure 62.
VDD Digital Inputs 250 W DGND Figure 62. Equivalent ESD Protection Circuits Submit Documentation Feedback 19 DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 PCB LAYOUT
The DAC8803 is a high-accuracy DAC that can have its performance compromised by grounding and printed circuit board (PCB) lead trace resistance. The 14-bit DAC8803 with a 10-V full-scale range has an LSB value of 610 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as 2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 m will cause 1 LSB of voltage drop. The preferred PCB layout for the DAC8803 is to have all AGNDX pins connected directly to an analog ground plane at the unit. The non-inverting input of each channel I/V converter should also either connect directly to the analog ground plane or have an individual sense trace back to the AGNDX pin connection. The feedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR drops from contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8803. Table 1. Control Logic Truth Table (1)
CS H L L L + H H H H H CLK X L + H L X X X X X LDAC H H H H H L H + H H RS H H H H H H H H L L MSB X X X X X X X X 0 H SERIAL SHIFT REGISTER No effect No effect Shift register data advanced one bit No effect No effect No effect No effect No effect No effect No effect Latched Latched Latched Latched Selected DAC updated with current SR contents Latched Latched Latched Latched data = 0000h Latched data = 2000h INPUT REGISTER DAC REGISTER Latched Latched Latched Latched Latched Transparent Latched Latched Latched data = 0000h Latched data = 2000h (1) + Positive logic transition; X = Do not care Table 2. Serial Input Register Data Format, Data Loaded MSB First (1)
Bit Data B15 (MSB) A1 B14 A0 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 (LSB) D0 (1) Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 3. Address Decode
A1 0 0 1 1 A0 0 1 0 1 DAC DECODE DAC A DAC B DAC C DAC D 20 Submit Documentation Feedback DAC8803
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SBAS340C ­ JANUARY 2005 ­ REVISED FEBRUARY 2006 APPLICATION INFORMATION
The DAC8803, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output IOUT is the inverse of the input reference voltage at VREF. Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 63. An additional external op amp A2 is added as a summing amp. In this circuit the first and second amps (A1 and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation (Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = -10 V to VOUT = 10 V.
V OUT + D *1 8192 V REF
10 kW 10 V 5 kW 10 kW (2) A2 OPA277 VOUT VREF -10 V < VOUT < +10 V VDD VREFX One Channel DAC8803 AGNDF AGNDX RFBX IOUTX A1 OPA277 Digital interface connections omitted for clarity. Figure 63. Four-Quadrant Multiplying Application Circuit Cross-Reference
The DAC8803 has an industry-standard pinout. Table 4 provides the cross-reference information. Table 4. Cross-Reference
SPECIFIED TEMPERATURE RANGE -40°C to +85°C PACKAGE DESCRIPTION 28-Lead MicroSOIC PACKAGE OPTION SSOP-28 CROSSREFERENCE PART AD5554BRS PRODUCT DAC8803IDB INL (LSB) ±1 DNL (LSB) ±1 Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2008 PACKAGING INFORMATION
Orderable Device DAC8803IDBR DAC8803IDBRG4 DAC8803IDBT DAC8803IDBTG4
(1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP SSOP SSOP SSOP Package Drawing DB DB DB DB Pins Package Eco Plan (2) Qty 28 28 28 28 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SSOP SSOP DB DB 28 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 16.4 16.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12.0 12.0 W Pin1 (mm) Quadrant 16.0 16.0 Q1 Q1 DAC8803IDBR DAC8803IDBT 2000 250 8.1 8.1 10.4 10.4 2.5 2.5 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jan-2009 *All dimensions are nominal Device DAC8803IDBR DAC8803IDBT Package Type SSOP SSOP Package Drawing DB DB Pins 28 28 SPQ 2000 250 Length (mm) 346.0 346.0 Width (mm) 346.0 346.0 Height (mm) 33.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE
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