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BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design
BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design
Mohan V. Dunga
1
, Chung-Hsun Lin
1
, Darsen D. Lu
1
,

Weize Xiong
2
, C. R. Cleavelin
2
, P. Patruno
3
,
Jiunn-Ren Hwang
4
, Fu-Liang Yang
4
, Ali M. Niknejad
1
and Chenming Hu
1

1
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA
2
Texas Instruments Inc., SiTD, Dallas, TX USA
3
SOITECH S.A., Bernin, France
4
Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu City, Taiwan
Tel: +1-510-643-2638, E-mail:
dunga@eecs.berkeley.edu


Abstract
A novel surface-potential based multi-gate FET (MG-FET)
compact model has been developed for mixed-signal design
applications. For the first time, a MG-FET model captures the
effect of finite body doping on the electrical behavior of MG-
FETs. A unique field penetration length model has been
developed to model the short channel effects in MG-FETs. A
multitude of physical effects such as poly-depletion effect and
quantum-mechanical effect (QME) have been incorporated. The
expressions for terminal currents and charges are
¶continuous
making the model suitable for mixed-signal design. The model
has been verified extensively with TCAD and experimental data.

Introduction
The improved short-channel effects (SCE) in multi-gate
FETs (MG-FET) due to the stronger electrostatic control from
multiple gates makes them an ideal candidate to extend CMOS
scaling [1]. To enable efficient MG-FET circuit design, an
accurate compact model for MG-FETs is necessary. Most of the
modeling efforts [2,3] are limited to undoped or lightly doped
body for double-gate FETs (DG-FET).
In this work, a new surface-potential based model is
developed which incorporates the effect of finite body doping on
the electrical characteristics of the transistor. Starting from a
symmetric DG-FET framework, the model is extended to tri-gate
FETs using 3-D modeling of SCE. Substrate current model
enables modeling of both SOI FinFETs [4,5], and bulk FinFETs
[6] (Fig.1). A full fledged compact model BSIM-MG has been
developed through incorporation of additional physical effects
and leakage currents. The model has been verified against TCAD
and experimental MG-FET data for long and short channel
lengths. Accurate fitting to drain current (I
d
), transconductance
(g
m
), g
m
-efficiency (g
m
/I
d
) and output conductance (g
ds
) are
observed indicating excellent model efficiency for digital and
analog design applications.
Core Model
Fig. 2 shows the schematic of DG-FET. Surface potential (
s
)
in the finite-doped body is obtained through a solution of the 1-D
Poissons equation using perturbation method [7]. For numerical
robustness, an analytical approximation to the resulting
transcendental
s
equation is implemented with an error limited
to few nano-Volts. The calculated
s
shows very good agreement
with TCAD [8] for a wide range of body doping (Fig. 3). Surface
potentials calculated at the source and drain end form the basis of
I-V and C-V models.

I-V model is obtained from drift-diffusion formulation.
By using a simplified expression for inversion charge, I
d
is
derived. The I-V model was verified against TCAD for a wide
range of body doping (Fig. 4(a)). A unique behavior of lightly
doped FinFETs is volume inversion. In subthreshold, band
bending in the body is minimal and the electronic potential is
nearly independent of body thickness (T
Si
) (Fig. 4(b)). As a
result, the subthreshold leakage is linearly proportional to T
Si
.
Fig. 4(c) shows that the core I-V model is able to capture the
volume inversion in DG-FETs.
Terminal charges and transcapacitances are derived using
current continuity in conjunction with Ward-Dutton charge
partition [9]. C-V model predicts very accurate transcapacitances
over different gate and drain voltages as seen in Fig. 5. At V
ds
=0,
C
sg
= C
dg
and C
gs
= C
gd
showing the inherent symmetry in the
model which is required for certain analog and RF applications.
The verification of core I-V and C-V model with TCAD (Fig. 3
Fig. 7) is done without the use of any fitting parameters.
Physical Effects
Numerous physical effects such as poly depletion (PDE),
QME, SCE and mobility degradation have been added over the
core model which can be activated when needed. For example,
by switching PDE model ON/OFF, I
d
can be obtained for poly-
gate/metal gate (Fig. 6). The degree of SCE depends on strength
of gate control which is modeled by a characteristic field
penetration length ( = f(T
ox
,T
si
)). Fig 7(a),(b) compares the
threshold voltage (V
th
) roll-off extracted from the model against
2-D TCAD results without the use of any fitting parameter. Good
scalability over T
ox
and T
si
down to 30nm channel length (L
g
) is
clearly visible. For tri-gate FETs, the physical location of
maximum I
d
leakage is different than DG-FETs (Fig. 7(c)),
which causes V
th
roll-off to increase as fin height (H
fin
) increases.
By making = f(T
ox
,T
si
,H
fin
), model scalability includes H
fin
(Fig.
7(d)) extending the DG-FET core model to tri-gate FETs. The
SCE model implementation captures V
th
roll-off, DIBL and
subthreshold slope degradation for short channel MG-FETs
simultaneously.
Leakage current mechanisms such as gate tunneling and gate-
induced drain leakage are also modeled. The substrate current
model comprising of impact ionization current and diode current
extends the 3-terminal SOI MG-FET model to 4-terminal bulk
MG-FET. BSIM-MG can model DG-FETs and tri-gate FETs
fabricated on either SOI wafers or bulk Si substrate making it a
truly versatile model.
Experimental Verification
The model is verified against two different FinFET
technologies SOI FinFETs and bulk FinFETs. BSIM-MG was
able to describe the trends in I
d
and its derivatives

for long and
short channel FETs for both technologies.

Important metrics for
analog design are g
m
, g
ds
and g
m
/I
d
. Fitting results to short channel
FETs and selected analog design metrics for long channel FETs
are shown for SOI FinFETs (Fig. 8) and bulk FinFETs (Fig. 9).
Conclusion
A full-fledged, versatile, surface-potential based multi-gate
FET model has been developed with several novel modeling
features. The agreement of core model with TCAD without any
fitting parameter demonstrates the inherent physical predictivity
and scalability of the model. BSIM-MG has also been verified
against experimental data (drain current and its derivatives)
demonstrating its applicability for mixed signal design.
References
[1] X. Huang, et al, Proc. IEDM Tech. Dig., p.67, 1999.
[2] Y. Taur et al., IEEE EDL, p.107, Feb 2004.
[3] G.D.J. Smit et al, IEDM Tech. Dig., p.175, 2006.
[4] W. Xiong, et al, Proc. DRC, p.39, 2006.
[5] F.-L. Yang, et al, Symp. VLSI Tech. Dig., p.104, 2002.
[6] T. Park, et al, Symp. VLSI Tech. Dig., p.135, 2003.
[7] M. V. Dunga, et al, IEEE TED, p.1971, 2006.
[8] Taurus-Device v. 2003 (Synopsys, Inc.).
[9] D. E. Ward, et al, IEEE JSSC, p. 703, 1978 -0.5
0.0
0.5
1.0
0.0
300.0µ
600.0µ
900.0µ
1.2m
GIDL
Vds=50mV
Vds=1V
Vds=50mV
Vds=1V
Lg = 90nm


D
r
ai
n C
u
r
r
e
n
t (
A
)
Gate Voltage (V)
1n
100n
10µ
1m

Fig. 5 Model predicts accurate transcapacitances as a
function of (a) gate voltage and (b) drain voltage. Model
symmetry can be seen at V
ds
=0 where C
dg(gd)
= C
sg(gs)

which is necessary for accurate analog simulations.
(a)
(b)
0.03
0.1
0.2
0.0
0.2
0.4
0.6
Tox = 2nm, Na = 1e15cm
-3
Vds=100mV


V
t
h
R
o
l
l
-o
f
f
(V)
Channel Length (µm)
Tsi = 10nm
Tsi = 15nm
Tsi = 20nm
Tsi = 25nm
Tsi = 30nm
Fig. 7 Scalability of SCE model has been demonstrated through threshold voltage roll-off for different (a) oxide
thickness and (b) body thickness for DG-FETs. (c) Leakage current path is different in tri-gate FETs due to 3D
effects. (d) SCE model also exhibits fin height scalability for tri-gate FETs (Symbols: TCAD, Lines: Model)
Fig. 9 Bulk FinFETs with moderate doping were fabricated with a TiN gate. Measured devices have T
Si
= 25nm and EOT = 1.95nm. Short channel
(L
g
=50nm) fitting to measured I
d
, I
sub
and g
ds
and long channel (L
g
= 0.97µm) g
m
and g
ds
are shown. (Symbols: measured data, Lines: model) The
model is able to describe both bulk FinFETs and SOI FinFETs.
(c) (d)
Fig. 6 PDE is accurately modeled.
Model predicts the degradation in
drain current in strong inversion
due to voltage drop in poly-gate.
0.50
0.75
1.00
1.25
1.50
0.0
0.2
0.4
0.6
0.8
1.0
Cdg
Csg
Cgg
Na = 3e18cm
-3
Vds = 1.5V
Symbols : TCAD
Lines : Model


N
o
rm
al
i
z
ed
C
a
pa
c
i
t
a
nc
e
Gate