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MemoryTen MemoryTen
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of
standard warranty. Production processing does not necessarily include
testing of all parameters.
MemoryTen
168-Pin DIMM (MO-161)
1.155 tall
Features
PC66-compliant, 168-pin, Dual in-line memory module (DIMM)
Utilizes 100 MHz SDRAM components
Unbuffered
64MB (8 Meg x 64), 128MB (16 Meg x 64)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/ precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode: Standard and Low Power
64ms, 4,096-cycle, (15.625µs) refresh interval
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
64U8S88-10KO9026 8 Meg X 64 SDRAM 168 Pin DIMM PC-66
128U16S88-10KO9026 16 Meg X 64 SDRAM 168 Pin DIMM PC-66
ALL SPECIFICATIONS FOR PRODUCTS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY
WITHOUT NOTICE.
MemoryTen
BP6866RA_PC-66.PDF
REV A
04-30-08
Parameter
64MB
128MB
Refresh Count
4K
4K
Device Banks
4 (BA0, BA1)
4 (BA0, BA1)
Device
Configuration
64Mb (8 Meg x 8)
64Mb (8 Meg x 8)
Row Addressing
4K (A0A11)
4K (A0A11)
Column
Addressing
512 (A0A8)
512 (A0A8)
Module Ranks
(S0#, S2#)
2 (S0#, S2#; S1#, S3#)
Representative example
1 PART NUMBER
MODULE DENSITY
CONFIGURATION
SYSTEM BUS SPEED
64U8S88-10KO9026
64MB
8 Meg x 64
66 MHz
128U16S88-10KO9026
128MB
16 Meg X 64
66 MHz
ORDERING INFORMATION
2 168-Pin DIMM Front
168-Pin DIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VSS
22
NC
43
VSS
64
VSS
85
VSS
106
NC
127
VSS
148
VSS
2
DQ0
23
VSS
44
NC
65
DQ21
86
DQ32
107
VSS
128
CKE0
149
DQ53
3
DQ1
24
NC
45
S2#
66
DQ22
87
DQ33
108
NC
129
S3#
150
DQ54
4
DQ2
25
NC
46
DQMB2
67
DQ23
88
DQ34
109
NC
130
DQMB6
151
DQ55
5
DQ3
26
VDD
47
DQMB3
68
VSS
89
DQ35
110
VDD
131
DQMB7
152
VSS
6
VDD
27
WE#
48
NC
69
DQ24
90
VDD
111
CAS#
132
NC
153
DQ56
7
DQ4
28
DQMB0
49
VDD
70
DQ25
91
DQ36
112
DQMB4
133
VDD
154
DQ57
8
DQ5
29
DQMB1
50
NC
71
DQ26
92
DQ37
113
DQMB5
134
NC
155
DQ58
9
DQ6
30
S0#
51
NC
72
DQ27
93
DQ38
114
S1#
135
NC
156
DQ59
10
DQ7
31
NC
52
NC
73
VDD
94
DQ39
115
RAS#
136
NC
157
VDD
11
DQ8
32
VSS
53
NC
74
DQ28
95
DQ40
116
VSS
137
NC
158
DQ60
12
VSS
33
A0
54
VSS
75
DQ29
96
VSS
117
A1
138
VSS
159
DQ61
13
DQ9
34
A2
55
DQ16
76
DQ30
97
DQ41
118
A3
139
DQ48
160
DQ62
14
DQ10
35
A4
56
DQ17
77
DQ31
98
DQ42
119
A5
140
DQ49
161
DQ63
15
DQ11
36
A6
57
DQ18
78
VSS
99
DQ43
120
A7
141
DQ50
162
VSS
16
DQ12
37
A8
58
DQ19
79
CK2
100
DQ44
121
A9
142
DQ51
163
CK3
17
DQ13
38
A10
59
VDD
80
NC
101
DQ45
122
BA0
143
VDD
164
NC
18
VDD
39
BA1
60
DQ20
81
NC
102
VDD
123
A11
144
DQ52
165
SA0
19
DQ14
40
VDD
61
NC
82
SDA
103
DQ46
124
VDD
145
NC
166
SA1
20
DQ15
41
VDD
62
NC
83
SCL
104
DQ47
125
CK1
146
NC
167
SA2
21
NC
42
CK0
63
CKE1
84
VDD
105
NC
126
A12
147
NC
168
VDD
168
85
1
84
C9
RP1
RP2
C10
RP5
RP6
RP8
C12
R1
R2
R4
C13
RP14
RP15
RP12
C15
RP11
RP9
C16
RP3
RP4
C11
RP7
R5
RP13
C14
RP31
RP10
R6
R3
U17
U1
U2
U4
U10
U12
U3
U9
U11
U20
U21
U14
U19
U18
U16
U15
U13
RP29
RP32
RP30
RP28
RP27
RP26
RP25
RP24
RP22
RP23
RP18
RP21
RP20
RP19
RP17 RP16
3 Pin Descriptions
Pin Numbers
Symbol
Type
Description
27, 111, 115
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
42, 79, 125, 163
CK0CK3
Input
Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the internal
burst counter and controls the output registers.
63, 128
CKE0, CKE1
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND OPERATION (burst access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during power-
down and self refresh modes, providing low standby power.
30, 45,114, 129
S0#S3#
Input
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S# is
registered HIGH. S# is considered part of the command code.
28, 29, 46, 47, 112, 113,
130, 131
DQMB0
DQMB7
Input
Input/Output mask: DQMB is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked
when DQMB is sampled HIGH during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when DQMB
is sampled HIGH during a READ cycle.
39, 122
BA0, BA1
Input
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
3338, 117121, 123, 126
A0A12
Input
Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective device bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command.
83
SCL
Input
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
165167
SA0SA2
Input
Presence-Detect address Inputs: These pins are used to configure the
presence-detect device.
25, 711, 1317, 1920,
5558, 60, 6567, 6972,
7477, 8689, 9195,
97101, 103104, 139142,
144, 149151,
153156,158161
DQ0DQ63
Input/
Output
Data I/O: Data bus.
82
SDA
Input/
Output
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
6, 18, 26, 40, 41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
VDD
Supply
Power supply: +3.3V ±0.3V.
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127,
138, 148,. 152, 162
VSS
Supply
Ground.
4 BLOCK DIAGRAM
S0
S1
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D0
DQMB0
DQM
D8
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D1
DQM
I/O 4
D9
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D2
DQM
I/O 4
D10
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D3
DQM
I/O 4
D11
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D4
DQMB4
DQM
D12
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D5
DQM
I/O 4
D13
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D6
DQM
I/O 4
D14
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB6
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D7
DQM
I/O 4
D15
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB7
VDD
VSS
D0 - D15
D0 - D15
A0 - AN
A0-AN: SDRAMS D0 - D15
# NOTE: ALL RESISTOR VALUES ARE 10 OHMS.
#
S2
S3
RAS
RAS: SDRAMS D0 - D15
CAS
CAS: SDRAMS D0 - D15
CKE0
CKE: SDRAMS D0 - D7
WE
WE: SDRAMS D0 - D15
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
* CLOCK WIRING
*CK0
CLOCK
INPUT
SDRAMS
*CK1
*CK2
*CK3
4 SDRAMS
4 SDRAMS
4 SDRAMS
4 SDRAMS
CKE1
CKE: SDRAMS D8 - D15
VDD
10K
* Wire per Clock Loading Table/Wiring Diagrams
NOTE: DQ wiring may differ than described in
this drawing, however DQ/DQMB/CKE/S
relationships must be maintained as shown.
BA0 - BAN
BA0-BAN: SDRAMS D0 - D15
A0
SERIAL PD
A1
A2
SA0
SA1
SA2
SCL
SDA
X64 SDRAM DIMM, 2 Banks with X8 SDRAMs
For 64U8S88-10KO9026 only install D0 - D7.
5 Capacitance
T
A
= 0 to 70
DD
= 3.3 V 0.3 V,
f = 1 MHz
DC Characteristics
T
V
V
V
A = 0 to 70 °C;
SS = 0 V;
DD, DDQ = 3.3 V ± 0.3 V
Module Characteristics
Limit Values
Parameter
Symbol min.
max.
Unit
Input high voltage
V
IH
2.0
Vcc+0.3
V
Input low voltage
V
IL
0.5
0.8
V
Output high voltage (
I
OUT
=