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Burn-in & Test Socket
Workshop
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TM Burn-in & Test Socket
Workshop
Session 1
Monday 3/08/04 8:30AM
PUSHING THE ENVELOPE
IC Power - The Influence And Impact Of Semiconductor
Technology
Marc Knox IBM Microelectronics
Reducing The Cost Of Test In Burn-in - An Integrated
Approach
Michael Noel Motorola SPS
Don VanOverloop Motorola SPS Allan Dobbin Motorola SPS
0.4mm Compression Mount BGA Burn-in Socket, Another
Breakthrough in Socket Technology
Helge Puhlmann Yamaichi Electronics
Kazuhiro Matsuda Yamaichi Electronics Jec Sangalang Yamaichi Electronics
Technical Program IC POWER
The INFLUENCE and
IMPACT of
SEMICONDUCTOR
TECHNOLOGY
Marc Knox
IBM Microelectronics
Burlington VT
BiTS 2004 INTRODUCTION
THE GOOD The CMOS Semiconductor marketplace is demanding
IC designs that are: Faster, smaller, more functional and lower in cost Conventional CMOS scaling has been able to maintain
trends which satisfy these demands
THE BAD AND THE UGLY The technology scaling that satisfies the performance
trends comes at a cost..........Increasing Power! Why is this the case? Will this go on forever? Where
does this leave test and burn-in? A base understanding of the semiconductor technology
which drives our industry is an important differentiator in our
business THE GOOD PART
CMOS SCALING BENEFITS Scaling is the primary driver in the gains made to date
in CMOS performance The industry has stayed close to, or ahead of, the
scaling predicted by Moore s Law Conventional scaling involves physical reduction of
transistor gate length, width and oxide dimensions as
well as power supply voltage Conventional scaling is becoming increasingly difficult
to realize Into the future, scaling takes the form of effective scaling with new materials and structures CMOS SCALING
PERFORMANCE, DENSITY TREND
Adopted from [1]
Y e a r o f I n t r o d u c t io n
2 0 0 0
2 0 0 2
2 0 0 4
2 0 0 6
2 0 0 8
F
r
equency on chip(GHz)
1
2
3
4
5
6
7
Transistors/cm
2
5 0
1 0 0
1 5 0
2 0 0
2 5 0
3 0 0
3 5 0
~ 40% increase/yr CMOS SCALING
PHYSICAL Tx DIMENSION
PHYSICAL GATE LENGTH
(High Performance Logic )
1
10
100
1000
1988
1991
1994
1996
1999
2001
2003
2005
2007
2013
G
A
TE LEN
G
TH
(
n
m
)
Adopted from [1] THE BAD AND THE UGLY PARTS
CMOS POWER IS NOT SCALING Conventional scaling sees transistor dimensions
shrinking at a high rate but supply voltage and
threshold voltage are decreasing at a slower rate The static DC leakage power trend is much steeper
than the AC switching power trend Leakage is on track to equal and exceed active power
in the application space For test and burn-in, this power is a huge concern We will continue to see substantial power increases if
performance gain trends are to continue on pace CMOS SCALING (or lack thereof)
VOLTAGE APPLIED
Chart courtesy of Roger Schmidt , IBM
Vdd - volts
0 .6
0 .7
0 .8
0 .9
1 .0
1 .1
1 .2
Vdd - volts
0 .6
0 .7
0 .8
0 .9
1 .0
1 .1
1 .2
Vdd - volts
0 .6
0 .7
0 .8
0 .9
1 .0
1 .1
1 .2
5% decrease/year CMOS SCALING (or lack thereof)
SYSTEM POWER
Chart courtesy of Roger Schmidt , IBM
Y e a r o f A n n o u n c e m e n t
1 9 5 0
1 9 6 0
1 9 7 0
1 9 8 0
1 9 9 0
2 0 0 0
2 0 1 0
Module Heat Flux
(watts/cm
2
)
0
2
4
6
8
1 0
1 2
1 4
B ip o la r
C M O S
V a c u u m
IB M 3 6 0
IB M 3 7 0
IB M 3 0 3 3
IB M E S 9 0 0 0
F u jits u V P 2 0 0 0
IB M 3 0 9 0 S
N T T
F u jits u M -7 8 0
IB M 3 0 9 0
C D C C y b e r 2 0 5
IB M 4 3 8 1
IB M 3 0 8 1
F u jits u M 3 8 0
IB M R Y 5
IB M G P
IB M R Y 6
A p a c h e
P u ls a r
M e rc e d
IB M R Y 7
IB M R Y 4
P e n tiu m II(D S IP )
T -R e x
S q u a d ro n s
P e n tiu m 4
M c k in le y WHY IS POWER NOT SCALING? CMOS is supposed to be low power .. right?
IN
OUT
Vdd
I
Vdd
0
Vg
Switching
I
Problem Occurs Here
(subthreshold region)
P
N
Superimposed
I/V Curves
N
P
Freehand Curves for Illustration (not to scale) WHY IS POWER NOT SCALING?
Tx Transfer Curve in the Sub Vt region The off transistor is never really fully off
Vt scales along with technology supply voltage (linear) Ioff is exponentially related to Vt in the SubVt region Ioff increases exponentially with lower supply voltage!!
Log I
ds
0
Vgs
Vt2
Vt
1
I
off 1
I
off 2 CMOS DC POWER ORIGINS
Main Leakage Components of Interest Gate Oxide Tunneling Current Channel Off Current Drain Induced Barrier
Lowering, Short Channel Effect, Narrow
Channel Effect, Gate Induced Drain Leakage
Source
Drain
Gate
2.
1.
. THE TRIPLE WHAMMY
AT ELEVATED CONDITIONS Most test and burn-in processes require some
form of elevated conditions These conditions produce higher currents
than are typically seen in the application Both voltage and temperature are
exponentially related to CMOS Ioff currents These additional currents are ON TOP OF the
increasing base power/current trends A true triple whammy! CMOS DC LEAKAGE Amps vs. Volts
(multiple individual parts)
1.30V
1.35V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
APPLIED VOLTAGE
20
40
60
80
100
120
140
160
CURRENT (A)
Large uP, Small Sample Characterization Data
Recent large uP design in IBM CMOS SOI @ BI Temp
The Slippery Slope HOW DESIGN INFLUENCES POWER Both system and chip level design choices play a role Design choices are ultimately dictated by system
requirements (power, reliability, speed, function) Historically, performance has been a key objective Power has become the counterpoint to performance Some examples of design influences/choices include: Technology in use (SOI, Bulk, copper, low K, etc.) Process centering (short = fast, long = slow) Number of low Vt devices allowed Oxide thickness Power Distribution (Voltage islands) System architecture (Clock throttling/gating, Pipeline
depth, Compute informed power management) System reliability (redundancy, ECC, FITs targets) LOW Vt USAGE & LINE CENTER
INFLUENCE ON STATIC POWER
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.01
0.1
1
10
100
1000
1 10 4
Ioffchip(A )
Leff
B IVolts, B I Tem p,
w / Low Vt
BI Volts, BI Tem p,wo/ Low Vt
U se Volts, BI Tem p,
w/ Low Vt
U se Volts, BI Tem p, wo/ Low Vt
IBM 8S2 Processor model chart courtesy of Andreas Bryant, IBM
(um) PROCESSING INFLUENCES
IC POWER All parts produced . in the same fabricator on the same line on the same tools to the same process

..are not exactly the same Deep submicron technology has large inherent
processing variations Scaling dictates smaller dimensions and larger relative
variations Power variation gets worse with conventional scaling Variations are amplified at accelerated conditions SAME PROCESS PRODUCES
WIDE RANGE OF SPEED/POWER
750
800
850
900
950
1000
Ring Oscillator Period (ns)
0
50
100
150
200
250
300
Power (W)
1.50 V
1.70 V
Burn-In Power vs. Inherent Speed
Large IBM uP Design (CMOS SOI process) THERMAL RUNAWAY Thermal runaway is a positive feedback phenomena
in which leakage current and temperature interact in
an exponential fashion with each other
Initial IC T
J
More Current
More Current
More Current
More Current
Higher Temperature
Higher Temperature
Higher Temperature
Higher Temperature CMOS DC LEAKAGE
POWER vs. TEMPERATURE
1.30V
1.35V
1.40
V
1.45V
1.50 V
1.55
V
1.60
V
1.65
V
Voltage (Volts)
0
50
100
150
200
250
300
Power (Watts)
140C
130C
120C
Recent Large uP Design in IBM CMOS SOI
Single Part Data @ 3 Temperatures THERMAL RUNAWAY Thermal runaway is not necessarily attributable to a
single root cause Thermal runaway contributors come from two
interdependent categories of influence
Chip influenced IC internal inherent characteristics and
parameters Design practices, circuit types, technology
employed, line center, etc. Tooling influenced IC external environment and parameters Thermal control, voltage control, thermal
interface, etc. THERMAL RUNAWAY
CHIP INFLUENCES Chip influenced thermal runaway is more likely to
occur with: Short channel hardware Minimum/sub-minimum ground rule design SOI technology Low Vt devices Low K dielectric use (thermal minor?) Current dense circuit areas (hot spots) Accelerated conditions CHIP LEAKAGE HOTSPOTS
(microprocessor logic cores in this case) TYPICAL THERMAL TEST CHIP
9 temperature se