PowerDAQ Lab PCI Digital I/O Boards Features
· 64 lines (5V/TTL) of I/O in 16-bit ports · Generate interrupts on any line · Four separate high-speed IRQ lines (100 ns) · Custom logic chip replaces obsolete 8255s and equivalents · Ideal for solid-state relays · User-defined power-up state in 16-bit groups (High, Low, Tri-stated) · 10-k onboard pull-down resistors for all I/Os · Onboard FIFO: 1k samples in/2k samples out · Two Enhanced Synchronous Serial Interface (ESSI) ports for high-speed devices such as codecs · Optional 192k-byte on-board SDRAM · Three 24-bit counter/timers · Port scan list · Start/stop external trigger line · Rigid 96-conductor pinless SCSI connector General Description
For applications that involve a high number of digital points, UEI offers four models in the PDL-DIO family with 64 I/O lines. Instead of following the industry trend of implementing discrete I/O with cumbersome and limiting 8255-type devices, we work with 16-bit line drivers under control of a DSP and custom logic. As a result, you no longer need to create external circuitry to guarantee power-on startup states; our software allows you to configure startup states in groups of 16-bit ports. You no longer need to design separate interrupt circuitry; our hardware comes with four high-speed interrupts waiting for you to use. The digital I/O lines are protected against electrostatic discharge and automatically detect shorts on power up. Besides digital I/O, the board features three 24-bit counter/timers as well as two high-speed ESSI (Enhanced Synchronous Serial Interface) ports. The onboard DSP and optimized PCI-bus interface also allow the card to optionally stream digital data to or from disk at rates as high as 1.6 MB/s and count frequency up to 16.5 MHz. It supports change detection, handshaking lines to clock parallel digital I/O and externally clocked pattern generation. P C I / I S A Distribution panels make all the board's I/O capabilities available for field connection. Further, an optional accessory (PDLDIO-CONN64-4) distributes the 64 digital I/O points into four sets of 16 lines through industry-standard 50-pin IDC connectors. They, in turn, attach directly to relay panels available from UEI and many other sources. The PDL-DIO is ideally suited for OEM applications. Optional SDRAM and a firmware development kit allow customers to develop their own DSP code based on examples provided in the SDK or use this memory as a buffer for I/O operations. H A R D W A R E FREE Software Included: · PowerDAQ Software Suite · PowerDAQ for Linux/RTLinux · ProfessorDAQ Lite Excel Add-In · Drivers for:
Windows/Linux, QNX (optional), LabVIEW, VEE/VEE OneLab, TestPoint, DasyLab, DIAdem, MATLAB/xPC Target PowerDAQ PDL-DIO Series Block Diagram United Electronic Industries, Inc. Fax: (781) 821-2891 1 www.PowerDAQ.com Tel: (781) 821-2890 PowerDAQ Lab PCI Digital I/O Boards Technical Specifications
DC Electrical Characteristics Over Operating Range
Parameter Input High Level Input Low Level Input High Current Input Low Current 3-State Output Current 3-State Output Current Short-Circuit Current Test conditions Guaranteed logic High level Guaranteed logic Low level VI = 5V VI = Gnd VO = 2.7V VO = 0.5V VO = Gnd (momentary) Result 2.0V min 0.8V max ±1 µA max ±1 µA max ±1 µA max ±1 µA max -80 mA min -140 mA typ -250 mA max 100 mV typ Output Drive Characteristics
Parameter Output Drive Current Output High Voltage Output High Voltage Output High Voltage Output Low Voltage I/O Power Off Leakage Test conditions VO = 2.5V IOH = -3 mA IOH = -15 mA IOH = -32 mA IOL = 64 mA VI/O 4.5V Result -32 mA per pin -180 mA per port 3.5V typ, 4.8V max 3.5V typ, 4.7V max 2.4V min, 3.0V typ 0.2V typ, 0.55V max ±1 µA max Input Hysteresis Counter/Timer
Parameter Prescaler Number of Channels Resolution Maximum Frequency Minimum Frequency Minimum Pulse Width Output High Level Output Low Level Protection Input Low Voltage Input High Voltage Value 1 (21-bit) 3 24 bits 16.5M S/s for external clock and 33M S/s for internal DSP clock 0.0000002 S/s for internal clock, no low limit for external clock 20 ns 2.0V min @ -4 mA 0.5V max @ 4 mA 7 kV ESD, ±30V overshoot/undershoot 0.0­0.8V 2.0­5.0V PowerDAQ PDL-DIO ESSI Male Connector (J4) ESSI Characteristics
The Motorola 56301 DSP contains two fast Enhanced Synchronous Serial Interfaces. The PowerDAQ DIO board allows access to both. Each ESSI port contains three transmitters and one receiver and has a maximum operational speed of 15M bits/sec. PowerDAQ PDL-DIO Digital I/O Connector (J1) PowerDAQ PDL-DIO Counter/Timers/IRQ Lines Male Connector (J3) Ordering Information
PDL-DIO-64.......................................64 digital I/O channels, 3 counter/timers, 2 ESSI ports, four high-speed IRQ lines (100 ns), SRAM* * optional United Electronic Industries, Inc. Tel: (781) 821-2890 2 www.PowerDAQ.com Fax: (781) 821-2891 PowerDAQ Lab PCI Digital I/O Boards PDL-DIO-64CT
Continuous High-Speed Digital Event Counter General Description Features
· Monitor high-speed digital inputs for long periods · Two 24-bit counters track different inputs · Peak input frequency 16.5 MHz With the PDL-DIO-64CT variation of our digital I/O board users can take · Send counter values to a memory at rates to 1.6 MHz advantage of special features available with the counter/timer subsys· Also operates as standard DIO Series card tem. They can count external events on two inputs continuously and uninterrupted, while periodically sending the count readings to system memory or a disk file. They can do this for as long as they like (as long as memory can accommodate more readings). In normal operation without the -CT version, users must stop a counter, read its value and then reactivate it to continue operation; this pause is no longer necessary. Users supply an external pulsed signal to the inputs of two 24-bit counters; the peak input frequency is approximately 16.5 MHz. At a userdefined intervals, at rates as high as 1.6 MHz, a third counter/timer issues a signal that triggers a read of the contents of each counter (there is a 30-nsec delay between reading the first and second counter) and then the subsystem sends this reading to the 1k-sample FIFO buffer on the DSP. Every time the buffer is half full (512 samples), the DSP sends the values to host memory or a disk file using Bus Mastering or DMA transfers. The counters continue incrementing until they reach their maximum count value (2^24 = 16,777,216 counts) at which time they roll over and start counting again from zero. When not being used in this special counting mode, the card functions similar to the standard PDL-DIO-64 card. Even better, the digital I/O lines are available for static I/O while the counters are working in CT mode. Ordering Information
PDL-DIO-64CT ...........................................64 digital I/O channels, high-speed event counts streaming (1.6M words/s), SRAM (optional) PDL-DIO-64ST
Continuous High-Speed Digital I/O Word Streaming General Description
For those applications that require a long, continuous stream of highspeed digital input or output words even when operating under an operating system such as Windows, the DSP-based PDL-DIO-64ST offers a powerful solution. With a configuration word you define the initial channel in an input- or output-channel sequence along with the total number of ports (that value must be a power of two: 1, 2, 4 or 8). Because each port supports 16 channels, the card can operate with as many as 64 digital I/O points in this mode. You can set these ports up as inputs or and outputs simultaneously. Features
· Stream digital words in or out for long periods without interruption · Flexibility in assigning I/O ports as inputs or outputs · Maximum input/output rate 1.6M words/sec · Stream both inputs and outputs simultaneously · Create outputs in Regenerate or Bus Master mode · Also operates as standard DIO Series card outputs, and the card allows the operation of both streaming inputs P C I / I S A H A R D W A R E All the inputs operate together at one rate, and all the outputs operate together at one rate, but the input and output rates need not be the same. You can clock these operations from either an internal or an external clock, and in either case the maximum rate for either digital inputs or digital outputs is 1.6M words/sec When the card reads the digital words, it sends the results continually into the 1k-sample FIFO buffer in the DSP. Every time the buffer is half full (512 samples), the DSP sends the values to host memory or a disk file using Bus Mastering or DMA transfers. When the card outputs digital words, it obtains data from one of two sources depending on the mode. In Regenerate mode, it continuously cycles through digital words stored in an onboard buffer (2k words standard with options as large as 64k words). In Buffered mode, you continuously download the words into the onboard memory in response to interrupt requests from the board. When generating digital outputs, the per-channel rate is the aggregate rate from system RAM or the disk file divided by the number of digital output channels. When not being used in this special counting mode, the card functions similar to the standard PDL-DIO-64 card. And when the digital I/O lines are working in this streaming fashion, the counter/timers are available to the user. Ordering Information
PDL-DIO-64ST...........................................64 digital I/O channels, high-speed pattern generation and digital streaming, SRAM (optional) PowerDAQ Lab PCI Digital I/O Boards PDL-DIO-64TS
Variable Programmable Timing Sequencer General Description Features
· Generate a continuous series of pulses or digital words · Create outputs on all I/O ports enabled as digital outputs · Regenerate and Buffered modes available · Controlled with a 100-MHz DSP In some applications, it's necessary to generate a continually running · Each pulse or word varies from 1 µsec to 16 776 sec in 20-nsec series of digital pulses or words with strictly defined time intervals, increments and the PDL-DIO-64TS Timing Sequencer board accomplishes this · Generates a optional CPU interrupt after execution of each task with ease. Although it is possible to generate a user-defined Timing Sequencer command digital pulse or output word with the standard PowerDAQ DIO boards, several factors come into play. First, you cannot generate a · Also operates as standard DIO Series card continual series of pulses of differing widths without having a small gap between them during which you reconfigure the digital-output subsystem with parameters for the following pulse. For some applications this gap is not acceptable. Furthermore, running high-speed digital outputs in Buffered mode requires considerable processor power, extensive interaction with a user program and the user must prepare a large amount of data to configure and control each output sequence. Using specialized firmware running on the counter/timer integrated into the onboard DSP chip (a 100-MHz Motorola 56301), UEI has overcome this hurdle. With the PDL-DIO-64TS you create a series of commands, each of which defines a precise time interval and the digital pattern to be generated during that interval. You store these commands in the form of entries in a Time Sequence List (TS List) that resides in an onboard buffer memory. The board supplies four 16-bit digital I/O ports, and when you have enabled one or more of them as outputs, an entry in the TS List defines the levels the selected digital output lines should assume (logic Hi or Lo) as well as exactly how long they should retain these states. That duration can range from 1 µsec to 16 776 sec with an accuracy of 20 nsec (time intervals longer than 0.5 sec require two entries to maintain that accuracy). After that time has elapsed, the card moves to the next entry in the TS List and immediately reconfigures its output lines accordingly. Following the execution of an entry in the TS List, the card can optionally send an interrupt to the host CPU. Note that it is possible to disable this special Timing Sequence feature and use the board as a standard PDL-DIO64 I/O card. The number of entries possible in the TS List depend upon the selected operating mode. In Regenerate mode, you place entries in the onboard DSP buffer memory, which varies from 2k bytes (holding 256 entries) to an option with 64k bytes (holding 8192 entries). You can elect to run through these entries just one time or step through them repeatedly in a continuous cycle. In Buffered mode, you continuously download TS List entries into onboard memory in response to interrupt requests from the board. The data is moved in blocks of 128 entries at a maximum rate of 50k entries/sec. Ordering Information
PDL-DIO-64TS ...........................................................................................64 digital I/O channels, variable programmable timing sequencer PD-64KMEM.................................................................................Memory option, expands number of entries to TS List to a total of 8192 United Electronic Industries, Inc. Tel: (781) 821-2890 4 www.PowerDAQ.com Fax: (781) 821-2891