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High-Efciency Envelope-Tracking W-CDMA Base-Station Amplier Using GaN HFETs
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
1
High-Efciency Envelope-Tracking W-CDMA
Base-Station Amplier Using GaN HFETs
Donald F. Kimball, Member, IEEE, Jinho Jeong, Member, IEEE, Chin Hsia, Paul Draxler, Member, IEEE,
Sandro Lanfranco, Walter Nagy, Kevin Linthicum, Lawrence E. Larson, Fellow, IEEE, and
Peter M. Asbeck, Fellow, IEEE
AbstractA
high-efciency
wideband
code-division
mul-
tiple-access (W-CDMA) base-station amplier is presented using
high-performance GaN heterostrucutre eld-effect transistors
to achieve high gain and efciency with good linearity. For high
efciency, class J/E operation was employed, which can attain up
to 80% efciency over a wide range of input powers and power
supply voltages. For nonconstant envelope input, the average
efciency is further increased by employing the envelope-tracking
architecture using a wide-bandwidth high-efciency envelope
amplier. The linearity of overall system is enhanced by digital
pre-distortion. The measured average power-added efciency
of the amplier is as high as 50.7% for a W-CDMA modulated
signal with peak-to-average power ratio of 7.67 dB at an average
output power of 37.2 W and gain of 10.0 dB. We believe that this
corresponds to the best efciency performance among reported
base-station power ampliers for W-CDMA. The measured error
vector magnitude is as low as 1.74% with adjacent channel leakage
ratio of
51.0 dBc at an offset frequency of 5 MHz.
Index TermsEfciency, envelope elimination and restoration
(EER), envelope tracking (ET), power amplier.
I. I
NTRODUCTION
I
N ADDITION to excellent linearity, high efciency is es-
sential for low-cost high reliability wideband code-division
multiple-access (W-CDMA) base-station power ampliers. Si
LDMOS has been a popular transistor choice for base-station
high-power ampliers since LDMOS technology can provide
reliable and cost-effective solutions [1]. However, in order to
obtain better linearity and efciency for third-generation (3G)
wireless base stations, intense research on high-voltage GaAs
heterojunction bipolar transistors (HBTs) [2] and eld-ef-
fect transistors (FETs) [3], as well as GaN heterostructure
Manuscript received May 30, 2006; revised August 10, 2006. This work was
supported in part by Nokia and by the University of California under the Dis-
covery Grant Program.
D. F. Kimball is with the California Institute for Telecommunications and
Information Technology, University of California at San Diego, La Jolla, CA
92093 USA (e-mail: dkimball@cwc.ucsd.edu).
J. Jeong, C. Hsia, L. E. Larson, and P. M. Asbeck are with the Department of
Electrical and Computer Engineering, University of California at San Diego, La
Jolla, CA 92093 USA (e-mail: jjeong@ece.ucsd.edu; asbeck@ece.ucsd.edu).
P. Draxler is with the Department of Electrical and Computer Engineering,
University of California at San Diego, La Jolla, CA 92092 USA, and also with
Qualcomm Inc., San Diego, CA 92121 USA.
S. Lanfranco is with the Nokia Corporation, 90630 Oulu, Finland.
W. Nagy and K. Linthicum are with the Nitronex Corporation, Raleigh, NC
27606 USA.
Color versions of Figs. 9, 10, 12, and 13 are available online at http://ieeex-
plore.ieee.org.
Digital Object Identier 10.1109/TMTT.2006.884685
eld-effect transistors (HFETs) [4], [5] has been carried out.
GaN HFETs can provide higher voltage operation and higher
power density at microwave frequencies than other high power
devices and thus are attractive for application to commercial
high-power base stations.
Recently, high-performance GaN HFETs on Si substrates
(instead of the more customary sapphire or siliconcarbide
substrates) have been reported, showing 150-W output power
with high linearity and high reliability for W-CDMA base-sta-
tion applications [5]. The use of this GaN power amplier
within an envelope-tracking (ET) architecture was recently
reported by the authors in [6]. This paper presents performance
characteristics of this amplier system, which employs a dy-
namic supply voltage for efciency enhancement. Section II
introduces the conguration of the overall ET system. The
high-efciency performance of the RF power amplier is
analyzed by ADS simulations showing class J/E waveforms.
Single-tone measurement results are also given in Section II.
The design concept for the envelope amplier is demonstrated
in Section II, along with measurement results. In Section III,
the measured performance of the overall ET power amplier
is illustrated including an instantaneous measurement of the
RF stage efciency, which demonstrates the essential char-
acteristics of the ET amplier-high-efciency operation of
the RF amplier over a wide output power range. The power
dissipation reduction within the transistor is also demonstrated
resulting from the ET operation, which improves the reliability
and longevity of the device.
II. ET B
ASE
-S
TATION
A
MPLIFIER
A. Description of ET Systems
The block diagram of the ET amplier used in this study is
shown in Fig. 1. The W-CDMA signal is generated in the digital
domain, and consists of an envelope signal as well as in-phase
(I) and quadrature (Q) IF signals. After up-conversion, the re-
sultant RF signal provides the input to the RF amplier, which
is time varying (unlike the case for the envelope elimination and
restoration (EER) architecture). The supply voltage for the RF
amplier is modulated by the amplied envelope signal through
an efcient wideband envelope amplier so that the RF ampli-
er keeps operating close to its saturated power region for all
envelope amplitudes to improve average efciency.
The average efciency of an ET power amplier strongly de-
pends on the peak-to-average power ratio (PAR) and probability
density function (PDF) of the modulated input signal since the
drain bias voltage varies in proportion to the amplitude of input
0018-9480/$20.00 � 2006 IEEE This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 1. Block diagram of ET base-station amplier including signal generation
and up/down conversion [6].
signal. It is challenging to maintain high efciency over a wide
range of drain bias due to the dependence of output capaci-
tance and transconductance on drain voltage. As a result, the
efciency of the RF amplier is usually optimized at the drain
bias voltage corresponding to the maximum PDF in order to pro-
vide the maximum average efciency under ET operation [7].
To deal with the high PAR problem, a de-cresting procedure
(adjustment of the PAR of the input signal) was employed.
This procedure was performed digitally on the envelope of
the signal to optimize the efciency, adjacent channel leakage
ratio (ACLR), and error vector magnitude (EVM) performance.
The original W-CDMA input signal with 9.8-dB PAR was
de-crested to have a PAR of 7.67 dB [7]. This reduction of PAR
helps to improve the average efciency of the RF amplier
and limits the dynamic range of the envelope amplier. The
procedure was carried out in the digital domain as follows. For
a baseband input signal
, where
and
represent the amplitude and phase of the th time sample,
respectively, an error vector
is calculated from
if
otherwise
where
is the maximum amplitude of the target PAR.
A new error vector
corresponding to local envelope
peaks is then obtained using
if
and
otherwise.
This signal is passed through a low-pass lter to obtain
. Finally, de-crested signal
is generated by
. This procedure can be iterated to
achieve the desired PAR. The degradation of EVM and spectral
shape due to de-cresting is minimized by optimizing the cutoff
frequency of the low-pass lter. Half the chip rate was used for
the bandwidth of low-pass lter in the W-CDMA signal.
To minimize distortion by the time-delay difference between
envelope and RF paths, which is known to be one of the major
distortion mechanisms in EER or ET systems [8], synchroniza-
tion is performed by maximizing the amplitude and phase corre-
lation between the input and down-converted output signals [9].
In addition to the differential delay, there are other sources of
nonlinearity in the ET amplier such as AMAM and AMPM
distortion created by the varying drain bias voltage. These are
called
AM and
PM